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Date:   Wed, 6 Sep 2017 09:11:55 -0700
From:   Tim Chen <tim.c.chen@...ux.intel.com>
To:     Josh Poimboeuf <jpoimboe@...hat.com>, x86@...nel.org
Cc:     linux-kernel@...r.kernel.org,
        Mathias Krause <minipli@...glemail.com>,
        Chandramouli Narayanan <mouli@...ux.intel.com>,
        Jussi Kivilinna <jussi.kivilinna@....fi>,
        Peter Zijlstra <peterz@...radead.org>,
        Herbert Xu <herbert@...dor.apana.org.au>,
        "David S. Miller" <davem@...emloft.net>,
        linux-crypto@...r.kernel.org, Eric Biggers <ebiggers@...gle.com>,
        Andy Lutomirski <luto@...nel.org>, Jiri Slaby <jslaby@...e.cz>
Subject: Re: [PATCH 06/12] x86/crypto: Fix RBP usage in sha1_avx2_x86_64_asm.S

On 08/29/2017 11:05 AM, Josh Poimboeuf wrote:
> Using RBP as a temporary register breaks frame pointer convention and
> breaks stack traces when unwinding from an interrupt in the crypto code.
> 
> Use R11 instead of RBP.  Since R11 isn't a callee-saved register, it
> doesn't need to be saved and restored on the stack.

These changes seem okay.

Thanks.

Tim

> 
> Reported-by: Eric Biggers <ebiggers@...gle.com>
> Reported-by: Peter Zijlstra <peterz@...radead.org>
> Signed-off-by: Josh Poimboeuf <jpoimboe@...hat.com>
> ---
>  arch/x86/crypto/sha1_avx2_x86_64_asm.S | 4 +---
>  1 file changed, 1 insertion(+), 3 deletions(-)
> 
> diff --git a/arch/x86/crypto/sha1_avx2_x86_64_asm.S b/arch/x86/crypto/sha1_avx2_x86_64_asm.S
> index 1eab79c9ac48..9f712a7dfd79 100644
> --- a/arch/x86/crypto/sha1_avx2_x86_64_asm.S
> +++ b/arch/x86/crypto/sha1_avx2_x86_64_asm.S
> @@ -89,7 +89,7 @@
>  #define	REG_RE	%rdx
>  #define	REG_RTA	%r12
>  #define	REG_RTB	%rbx
> -#define	REG_T1	%ebp
> +#define	REG_T1	%r11d
>  #define	xmm_mov	vmovups
>  #define	avx2_zeroupper	vzeroupper
>  #define	RND_F1	1
> @@ -637,7 +637,6 @@ _loop3:
>  	ENTRY(\name)
>  
>  	push	%rbx
> -	push	%rbp
>  	push	%r12
>  	push	%r13
>  	push	%r14
> @@ -673,7 +672,6 @@ _loop3:
>  	pop	%r14
>  	pop	%r13
>  	pop	%r12
> -	pop	%rbp
>  	pop	%rbx
>  
>  	ret
> 

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