[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20170911201920.GA5983@lunn.ch>
Date: Mon, 11 Sep 2017 22:19:20 +0200
From: Andrew Lunn <andrew@...n.ch>
To: Corentin Labbe <clabbe.montjoie@...il.com>
Cc: robh+dt@...nel.org, mark.rutland@....com,
maxime.ripard@...e-electrons.com, wens@...e.org,
linux@...linux.org.uk, catalin.marinas@....com,
will.deacon@....com, peppe.cavallaro@...com,
alexandre.torgue@...com, f.fainelli@...il.com,
netdev@...r.kernel.org, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v5 10/10] net: stmmac: dwmac-sun8i: Handle
integrated/external MDIOs
> Even with CLK_BUS_EPHY/RST_BUS_EPHY enabled, the MAC reset timeout.
> So no the CLK/RST are really for the PHY.
Thanks for trying that.
You said it was probably during scanning of the bus it times out. What
address is causing the timeout? 0 or 1? If the internal bus can only
have one PHY on it, maybe we need to set bus->phy_mask to 0x1?
Andrew
Powered by blists - more mailing lists