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Date: Tue, 12 Sep 2017 17:07:51 +0800 From: Chaotian Jing <chaotian.jing@...iatek.com> To: Ulf Hansson <ulf.hansson@...aro.org> CC: Rob Herring <robh+dt@...nel.org>, Mark Rutland <mark.rutland@....com>, Matthias Brugger <matthias.bgg@...il.com>, Catalin Marinas <catalin.marinas@....com>, Will Deacon <will.deacon@....com>, Chaotian Jing <chaotian.jing@...iatek.com>, yong mao <yong.mao@...iatek.com>, Linus Walleij <linus.walleij@...aro.org>, Javier Martinez Canillas <javier@....samsung.com>, Heiner Kallweit <hkallweit1@...il.com>, Phong LE <ple@...libre.com>, <linux-mmc@...r.kernel.org>, <devicetree@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>, <linux-mediatek@...ts.infradead.org>, <linux-kernel@...r.kernel.org>, <srv_heupstream@...iatek.com> Subject: [PATCH 11/12] mmc: mediatek: improve eMMC hs400 mode read performance enlarge outstanding value to improve read performance Signed-off-by: Chaotian Jing <chaotian.jing@...iatek.com> --- drivers/mmc/host/mtk-sd.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c index 3328d59..49d4d79 100644 --- a/drivers/mmc/host/mtk-sd.c +++ b/drivers/mmc/host/mtk-sd.c @@ -81,6 +81,7 @@ #define PAD_DS_TUNE 0x188 #define PAD_CMD_TUNE 0x18c #define EMMC50_CFG0 0x208 +#define EMMC50_CFG3 0x220 #define SDC_FIFO_CFG 0x228 /*--------------------------------------------------------------------------*/ @@ -249,6 +250,8 @@ #define EMMC50_CFG_CRCSTS_EDGE (0x1 << 3) /* RW */ #define EMMC50_CFG_CFCSTS_SEL (0x1 << 4) /* RW */ +#define EMMC50_CFG3_OUTS_WR (0x1f << 0) /* RW */ + #define SDC_FIFO_CFG_WRVALIDSEL (0x1 << 24) /* RW */ #define SDC_FIFO_CFG_RDVALIDSEL (0x1 << 25) /* RW */ @@ -318,6 +321,7 @@ struct msdc_save_para { u32 pad_ds_tune; u32 pad_cmd_tune; u32 emmc50_cfg0; + u32 emmc50_cfg3; u32 sdc_fifo_cfg; }; @@ -1757,6 +1761,9 @@ static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE); /* hs400 mode must set it to 0 */ sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS); + /* to improve read performance, set outstanding to 2 */ + sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2); + return 0; } @@ -2010,6 +2017,7 @@ static void msdc_save_reg(struct msdc_host *host) host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE); host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0); + host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3); host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG); } @@ -2029,6 +2037,7 @@ static void msdc_restore_reg(struct msdc_host *host) writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE); writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE); writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0); + writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3); writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG); } -- 1.8.1.1.dirty
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