linux-kernel - [RESEND PATCH] ARM: dts: ls1021a: Add support for QSPI with ls1021a SoC

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Message-Id: <20170912064925.24571-1-sz.lin@moxa.com>
Date:   Tue, 12 Sep 2017 14:49:25 +0800
From:   SZ Lin <sz.lin@...a.com>
To:     unlisted-recipients:; (no To-header on input)
Cc:     Minghuan.Lian@....com, Zhiqiang.Hou@....com, andy.tang@....com,
        yi.sheng.lin@....com, SZ Lin <sz.lin@...a.com>,
        Rob Herring <robh+dt@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Russell King <linux@...linux.org.uk>,
        devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-kernel@...r.kernel.org
Subject: [RESEND PATCH] ARM: dts: ls1021a: Add support for QSPI with ls1021a SoC

Add QSPI node support, and this function is disabled by default
This setting could be overwritten in board-level definitions

Signed-off-by: SZ Lin <sz.lin@...a.com>
---
 arch/arm/boot/dts/ls1021a.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 7bb9df2c1460..9da876e47810 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -154,6 +154,20 @@
 			big-endian;
 		};
 
+		qspi: quadspi@...0000 {
+			compatible = "fsl,ls1021a-qspi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x0 0x1550000 0x0 0x10000>,
+			      <0x0 0x40000000 0x0 0x40000000>;
+			reg-names = "QuadSPI", "QuadSPI-memory";
+			interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
+			clock-names = "qspi_en", "qspi";
+			clocks = <&clockgen 4 1>, <&clockgen 4 1>;
+			big-endian;
+			status = "disabled";
+		};
+
 		esdhc: esdhc@...0000 {
 			compatible = "fsl,esdhc";
 			reg = <0x0 0x1560000 0x0 0x10000>;
-- 
2.14.1