linux-kernel - Re: [PATCH v2 00/10] spi-nor: intel-spi: Various fixes and enhancements

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Wed, 13 Sep 2017 10:11:21 +0800
From:   Bin Meng <bmeng.cn@...il.com>
To:     Joakim Tjernlund <Joakim.Tjernlund@...inera.com>
Cc:     "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "linux-mtd@...ts.infradead.org" <linux-mtd@...ts.infradead.org>,
        "mika.westerberg@...ux.intel.com" <mika.westerberg@...ux.intel.com>,
        "cyrille.pitchen@...ev4u.fr" <cyrille.pitchen@...ev4u.fr>,
        "dwmw2@...radead.org" <dwmw2@...radead.org>,
        "computersforpeace@...il.com" <computersforpeace@...il.com>,
        "boris.brezillon@...e-electrons.com" 
        <boris.brezillon@...e-electrons.com>,
        "marek.vasut@...il.com" <marek.vasut@...il.com>,
        "richard@....at" <richard@....at>, "sr@...x.de" <sr@...x.de>
Subject: Re: [PATCH v2 00/10] spi-nor: intel-spi: Various fixes and enhancements

Hi Joakim,

On Tue, Sep 12, 2017 at 1:44 AM, Joakim Tjernlund
<Joakim.Tjernlund@...inera.com> wrote:
> On Mon, 2017-09-11 at 02:41 -0700, Bin Meng wrote:
>> This series does several bug fixes and clean ups against the intel-spi
>> spi-nor driver, as well as enhancements to make the driver independent
>> on the underlying BIOS/bootloader.
>>
>> At present the driver uses the HW sequencer for the read/write/erase on
>> all supported platforms, read_reg/write_reg for BXT, and the SW sequencer
>> for read_reg/write_reg for BYT/LPT. The way the driver uses the HW and SW
>> sequencer relies on some programmed register settings and hence creates
>> unneeded dependencies with the underlying BIOS/bootloader. For example,
>> the driver unfortunately does not work as expected when booting from
>> Intel Baytrail FSP based bootloaders like U-Boot, as the Baytrail FSP
>> does not set up some SPI controller settings to make the driver happy.
>> Now such limitation has been removed with this series.
>
> Hi Bin
>
> Just starting to test these on Rangeley and got a question: We have two SPI flashes on CS0 resp. CS1
> and the mtd driver seems to only map the first of those flashes. Is this intentional or
> are we missing something?
>

All the boards I have tested only have one SPI flash. Mika, any comments?

Regards,
Bin