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Date: Thu, 14 Sep 2017 15:51:06 +0000 From: "Levin, Alexander (Sasha Levin)" <alexander.levin@...izon.com> To: "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>, "stable@...r.kernel.org" <stable@...r.kernel.org> Cc: Icenowy Zheng <icenowy@...c.xyz>, Maxime Ripard <maxime.ripard@...e-electrons.com>, "Levin, Alexander (Sasha Levin)" <alexander.levin@...izon.com> Subject: [PATCH for 4.9 07/59] clk: sunxi-ng: set the parent rate when adjustin CPUX clock on A33 From: Icenowy Zheng <icenowy@...c.xyz> [ Upstream commit bb021cda2ccf45ee9470bf0f8c55323ad1c761ae ] The CPUX clock on A33, which is for the Cortex-A7 cores, is designed to be changeable by changing the rate of PLL_CPUX. Add CLK_SET_RATE_PARENT flag to this clock. Signed-off-by: Icenowy Zheng <icenowy@...c.xyz> Signed-off-by: Maxime Ripard <maxime.ripard@...e-electrons.com> Signed-off-by: Sasha Levin <alexander.levin@...izon.com> --- drivers/clk/sunxi-ng/ccu-sun8i-a33.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c index 9bd1f78a0547..d54e5db3959a 100644 --- a/drivers/clk/sunxi-ng/ccu-sun8i-a33.c +++ b/drivers/clk/sunxi-ng/ccu-sun8i-a33.c @@ -170,7 +170,7 @@ static SUNXI_CCU_N_WITH_GATE_LOCK(pll_ddr1_clk, "pll-ddr1", static const char * const cpux_parents[] = { "osc32k", "osc24M", "pll-cpux" , "pll-cpux" }; static SUNXI_CCU_MUX(cpux_clk, "cpux", cpux_parents, - 0x050, 16, 2, CLK_IS_CRITICAL); + 0x050, 16, 2, CLK_IS_CRITICAL | CLK_SET_RATE_PARENT); static SUNXI_CCU_M(axi_clk, "axi", "cpux", 0x050, 0, 2, 0); -- 2.11.0
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