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Message-ID: <tip-6a707c0e451cb8d86943b840939e2ed881b8023e@git.kernel.org>
Date: Fri, 15 Sep 2017 01:45:42 -0700
From: tip-bot for Borislav Petkov <tipbot@...or.com>
To: linux-tip-commits@...r.kernel.org
Cc: hpa@...or.com, linux-kernel@...r.kernel.org, bp@...e.de,
torvalds@...ux-foundation.org, tglx@...utronix.de,
peterz@...radead.org, mingo@...nel.org, dzickus@...hat.com,
sherry.hurwitz@....com
Subject: [tip:x86/urgent] x86/cpu/AMD: Fix erratum 1076 (CPB bit)
Commit-ID: 6a707c0e451cb8d86943b840939e2ed881b8023e
Gitweb: http://git.kernel.org/tip/6a707c0e451cb8d86943b840939e2ed881b8023e
Author: Borislav Petkov <bp@...e.de>
AuthorDate: Thu, 7 Sep 2017 19:08:21 +0200
Committer: Ingo Molnar <mingo@...nel.org>
CommitDate: Fri, 15 Sep 2017 07:44:50 +0200
x86/cpu/AMD: Fix erratum 1076 (CPB bit)
CPUID Fn8000_0007_EDX[CPB] is wrongly 0 on models up to B1. But they do
support CPB (AMD's Core Performance Boosting cpufreq CPU feature), so fix that.
Signed-off-by: Borislav Petkov <bp@...e.de>
Reviewed-by: Don Zickus <dzickus@...hat.com>
Cc: Linus Torvalds <torvalds@...ux-foundation.org>
Cc: Peter Zijlstra <peterz@...radead.org>
Cc: Sherry Hurwitz <sherry.hurwitz@....com>
Cc: Thomas Gleixner <tglx@...utronix.de>
Link: http://lkml.kernel.org/r/20170907170821.16021-1-bp@alien8.de
Signed-off-by: Ingo Molnar <mingo@...nel.org>
---
arch/x86/kernel/cpu/amd.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 9862e2c..d58184b 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -763,6 +763,16 @@ static void init_amd_bd(struct cpuinfo_x86 *c)
}
}
+static void init_amd_zn(struct cpuinfo_x86 *c)
+{
+ /*
+ * Fix erratum 1076: CPB feature bit not being set in CPUID. It affects
+ * all up to and including B1.
+ */
+ if (c->x86_model <= 1 && c->x86_mask <= 1)
+ set_cpu_cap(c, X86_FEATURE_CPB);
+}
+
static void init_amd(struct cpuinfo_x86 *c)
{
early_init_amd(c);
@@ -791,6 +801,7 @@ static void init_amd(struct cpuinfo_x86 *c)
case 0x10: init_amd_gh(c); break;
case 0x12: init_amd_ln(c); break;
case 0x15: init_amd_bd(c); break;
+ case 0x17: init_amd_zn(c); break;
}
/* Enable workaround for FXSAVE leak */
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