linux-kernel - Re: [PATCH] crypto: s5p-sss: Add HASH support for Exynos

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Date:   Fri, 15 Sep 2017 17:31:10 +0800
From:   kbuild test robot <lkp@...el.com>
To:     Kamil Konieczny <k.konieczny@...tner.samsung.com>
Cc:     kbuild-all@...org, linux-crypto@...r.kernel.org,
        Krzysztof Kozlowski <krzk@...nel.org>,
        Herbert Xu <herbert@...dor.apana.org.au>,
        Vladimir Zapolskiy <vz@...ia.com>,
        linux-samsung-soc@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] crypto: s5p-sss: Add HASH support for Exynos

Hi Kamil,

[auto build test WARNING on cryptodev/master]
[also build test WARNING on v4.13 next-20170915]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Kamil-Konieczny/crypto-s5p-sss-Add-HASH-support-for-Exynos/20170915-161309
base:   https://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6.git master
config: tile-allmodconfig (attached as .config)
compiler: tilegx-linux-gcc (GCC) 4.6.2
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        make.cross ARCH=tile 

All warnings (new ones prefixed by >>):

   drivers//crypto/s5p-sss.c: In function 's5p_hash_xmit_dma':
>> drivers//crypto/s5p-sss.c:1153:2: warning: format '%d' expects argument of type 'int', but argument 5 has type 'size_t' [-Wformat]

vim +1153 drivers//crypto/s5p-sss.c

  1131	
  1132	/**
  1133	 * s5p_hash_xmit_dma - start DMA hash processing
  1134	 * @dd:		secss device
  1135	 * @length:	length for request
  1136	 * @final:	0=not final
  1137	 *
  1138	 * Map ctx->sg into DMA_TO_DEVICE,
  1139	 * remember sg and cnt in device dd->hash_sg_iter, dd->hash_sg_cnt
  1140	 * so it can be used in loop inside irq handler.
  1141	 * Update ctx->digcnt, need this to keep number of processed bytes
  1142	 * for last final/finup request.
  1143	 * Set dma address and length, this starts DMA,
  1144	 * return with -EINPROGRESS.
  1145	 * HW HASH block will issue signal for irq handler.
  1146	 */
  1147	static int s5p_hash_xmit_dma(struct s5p_aes_dev *dd, size_t length,
  1148				      int final)
  1149	{
  1150		struct s5p_hash_reqctx *ctx = ahash_request_ctx(dd->hash_req);
  1151		int cnt;
  1152	
> 1153		dev_dbg(dd->dev, "xmit_dma: digcnt: %lld, length: %d, final: %d\n",
  1154							ctx->digcnt, length, final);
  1155	
  1156		cnt = dma_map_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE);
  1157		if (!cnt) {
  1158			dev_err(dd->dev, "dma_map_sg error\n");
  1159			set_bit(HASH_FLAGS_ERROR, &ctx->flags);
  1160			return -EINVAL;
  1161		}
  1162	
  1163		FLOW_LOG("xmit_dma");
  1164		set_bit(HASH_FLAGS_DMA_ACTIVE, &dd->hash_flags);
  1165	
  1166		dd->hash_sg_iter = ctx->sg;
  1167		dd->hash_sg_cnt = cnt;
  1168		FLOW_LOG("xmit_dma cnt=%d final=%d len=%d", cnt, final, length);
  1169	
  1170		s5p_hash_write_ctrl(dd, length, final);
  1171	
  1172		/* update digcnt in request */
  1173		ctx->digcnt += length;
  1174		ctx->total -= length;
  1175	
  1176		/* catch last interrupt */
  1177		if (final)
  1178			set_bit(HASH_FLAGS_FINAL, &dd->hash_flags);
  1179	
  1180		s5p_set_dma_hashdata(dd, dd->hash_sg_iter); /* DMA starts */
  1181	
  1182		return -EINPROGRESS;
  1183	}
  1184	

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