linux-kernel - Re: [PATCH for 4.9 39/59] arm: dts: mt2701: Add subsystem clock controller device nodes

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Date:   Fri, 15 Sep 2017 13:15:43 +0200
From:   Matthias Brugger <matthias.bgg@...il.com>
To:     "Levin, Alexander (Sasha Levin)" <alexander.levin@...izon.com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "stable@...r.kernel.org" <stable@...r.kernel.org>
Cc:     James Liao <jamesjj.liao@...iatek.com>
Subject: Re: [PATCH for 4.9 39/59] arm: dts: mt2701: Add subsystem clock
 controller device nodes



On 09/14/2017 05:51 PM, Levin, Alexander (Sasha Levin) wrote:
> From: James Liao <jamesjj.liao@...iatek.com>
> 
> [ Upstream commit f235c7e7a75325f28a33559a71f25a0eca6112db ]
> 
> Add MT2701 subsystem clock controllers, inlcude mmsys, imgsys,
> vdecsys, hifsys, ethsys and bdpsys.
> 
> Signed-off-by: James Liao <jamesjj.liao@...iatek.com>
> Signed-off-by: Matthias Brugger <matthias.bgg@...il.com>
> Signed-off-by: Sasha Levin <alexander.levin@...izon.com>
> ---
>   arch/arm/boot/dts/mt2701.dtsi | 36 ++++++++++++++++++++++++++++++++++++
>   1 file changed, 36 insertions(+)
> 

It's not clear to me which bug in v4.9.y you are fixing with this. Can you 
please explain.

Thanks,
Matthias

> diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
> index 18596a2c58a1..77c6b931dc24 100644
> --- a/arch/arm/boot/dts/mt2701.dtsi
> +++ b/arch/arm/boot/dts/mt2701.dtsi
> @@ -174,4 +174,40 @@
>   		clocks = <&uart_clk>;
>   		status = "disabled";
>   	};
> +
> +	mmsys: syscon@...00000 {
> +		compatible = "mediatek,mt2701-mmsys", "syscon";
> +		reg = <0 0x14000000 0 0x1000>;
> +		#clock-cells = <1>;
> +	};
> +
> +	imgsys: syscon@...00000 {
> +		compatible = "mediatek,mt2701-imgsys", "syscon";
> +		reg = <0 0x15000000 0 0x1000>;
> +		#clock-cells = <1>;
> +	};
> +
> +	vdecsys: syscon@...00000 {
> +		compatible = "mediatek,mt2701-vdecsys", "syscon";
> +		reg = <0 0x16000000 0 0x1000>;
> +		#clock-cells = <1>;
> +	};
> +
> +	hifsys: syscon@...00000 {
> +		compatible = "mediatek,mt2701-hifsys", "syscon";
> +		reg = <0 0x1a000000 0 0x1000>;
> +		#clock-cells = <1>;
> +	};
> +
> +	ethsys: syscon@...00000 {
> +		compatible = "mediatek,mt2701-ethsys", "syscon";
> +		reg = <0 0x1b000000 0 0x1000>;
> +		#clock-cells = <1>;
> +	};
> +
> +	bdpsys: syscon@...00000 {
> +		compatible = "mediatek,mt2701-bdpsys", "syscon";
> +		reg = <0 0x1c000000 0 0x1000>;
> +		#clock-cells = <1>;
> +	};
>   };
>