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Date: Sun, 17 Sep 2017 22:20:51 -0700 From: Christoph Hellwig <hch@...radead.org> To: Huacai Chen <chenhc@...ote.com> Cc: "James E . J . Bottomley" <jejb@...ux.vnet.ibm.com>, "Martin K . Petersen" <martin.petersen@...cle.com>, Andrew Morton <akpm@...ux-foundation.org>, Fuxin Zhang <zhangfx@...ote.com>, linux-scsi@...r.kernel.org, linux-kernel@...r.kernel.org, stable@...r.kernel.org Subject: Re: [PATCH V5 3/3] scsi: Align queue to ARCH_DMA_MINALIGN in non-coherent DMA mode Please send all patches in the series to the same to and cc lists. On Mon, Sep 18, 2017 at 12:22:54PM +0800, Huacai Chen wrote: > In non-coherent DMA mode, kernel uses cache flushing operations to > maintain I/O coherency, so scsi's block queue should be aligned to > ARCH_DMA_MINALIGN. Otherwise, it will cause data corruption, at least > on MIPS: > > Step 1, dma_map_single > Step 2, cache_invalidate (no writeback) > Step 3, dma_from_device > Step 4, dma_unmap_single > > If a DMA buffer and a kernel structure share a same cache line, and if > the kernel structure has dirty data, cache_invalidate (no writeback) > will cause data lost. And as said before we must _always_ align to dma_get_cache_alignment. This is even documented in Documentation/DMA-API.txt: ------------------------------ snip ------------------------------ int dma_get_cache_alignment(void) Returns the processor cache alignment. This is the absolute minimum alignment *and* width that you must observe when either mapping memory or doing partial flushes. ------------------------------ snip ------------------------------ > + if (device_is_coherent(dev)) > + blk_queue_dma_alignment(q, 0x04 - 1); > + else > + blk_queue_dma_alignment(q, dma_get_cache_alignment() - 1); So as said before this should become something like: blk_queue_dma_alignment(q, max(0x04, dma_get_cache_alignment()) - 1);
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