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Date: Wed, 20 Sep 2017 15:46:14 +0300 From: Mikko Perttunen <cyndis@...si.fi> To: Krishna Reddy <vdumpa@...dia.com>, robh+dt@...nel.org, mark.rutland@....com, catalin.marinas@....com, will.deacon@....com, thierry.reding@...il.com, jonathanh@...dia.com, josephl@...dia.com, acourbot@...dia.com, mperttunen@...dia.com, devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, linux-tegra@...r.kernel.org, linux-kernel@...r.kernel.org Subject: Re: [PATCH] arm64: tegra: Add SMMU node for Tegra186 Reviewed-by: Mikko Perttunen <mperttunen@...dia.com> Tested-by: Mikko Perttunen <mperttunen@...dia.com> Tested to work with Host1x :) I noticed a slight difference with downstream where downstream has global interrupts 170 and 171 - but looks like the latter is for secure faults which we should never get so this way seems more correct. Thanks, Mikko On 14.09.2017 02:01, Krishna Reddy wrote: > Add the DT node for ARM SMMU on Tegra186. > > Signed-off-by: Krishna Reddy <vdumpa@...dia.com> > --- > arch/arm64/boot/dts/nvidia/tegra186.dtsi | 73 ++++++++++++++++++++++++++++++++ > 1 file changed, 73 insertions(+) > > diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi > index 0b0552c9f7dd..e2c3ad203c93 100644 > --- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi > +++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi > @@ -355,6 +355,79 @@ > nvidia,bpmp = <&bpmp>; > }; > > + smmu: iommu@...00000 { > + compatible = "arm,mmu-500"; > + reg = <0 0x12000000 0 0x800000>; > + #global-interrupts = <1>; > + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; > + #iommu-cells = <1>; > + stream-match-mask = <0x7F80>; > + }; > + > gpu@...00000 { > compatible = "nvidia,gp10b"; > reg = <0x0 0x17000000 0x0 0x1000000>, >
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