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Message-Id: <20170920193831.20268-4-jernej.skrabec@siol.net>
Date: Wed, 20 Sep 2017 21:38:27 +0200
From: Jernej Skrabec <jernej.skrabec@...l.net>
To: maxime.ripard@...e-electrons.com, wens@...e.org
Cc: Laurent.pinchart@...asonboard.com, narmstrong@...libre.com,
dri-devel@...ts.freedesktop.org, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-clk@...r.kernel.org, icenowy@...c.io,
linux-sunxi@...glegroups.com
Subject: [RFC PATCH 3/7] clk: sunxi: Add CLK_SET_RATE_PARENT flag for H3 HDMI clock
When setting the HDMI clock of H3, the PLL_VIDEO clock needs to be set.
Add CLK_SET_RATE_PARENT flag for H3 HDMI clock.
Signed-off-by: Jernej Skrabec <jernej.skrabec@...l.net>
Signed-off-by: Icenowy Zheng <icenowy@...c.io>
---
drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
index 7a222ff1ad0a..36224ba93f9d 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
@@ -474,7 +474,7 @@ static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",
static const char * const hdmi_parents[] = { "pll-video" };
static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
- 0x150, 0, 4, 24, 2, BIT(31), 0);
+ 0x150, 0, 4, 24, 2, BIT(31), CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M",
0x154, BIT(31), 0);
--
2.14.1
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