linux-kernel - Re: [PATCH v2] Documentation: rewrite confusing statement about memory barriers

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-Id: <20170921195058.GM3521@linux.vnet.ibm.com>
Date:   Thu, 21 Sep 2017 12:50:58 -0700
From:   "Paul E. McKenney" <paulmck@...ux.vnet.ibm.com>
To:     "Guilherme G. Piccoli" <gpiccoli@...ux.vnet.ibm.com>
Cc:     linux-doc@...r.kernel.org, linux-kernel@...r.kernel.org,
        corbet@....net
Subject: Re: [PATCH v2] Documentation: rewrite confusing statement about
 memory barriers

On Thu, Sep 21, 2017 at 04:29:01PM -0300, Guilherme G. Piccoli wrote:
> In this specific portion of the write memory barriers description,
> the documentation mentions sequential order of stores, which is
> confusing since sequential ordering is not guaranteed.
> 
> This patch tries to improve the doc in order to avoid any
> mis-understanding.
> 
> Cc: Paul E. McKenney <paulmck@...ux.vnet.ibm.com>
> Signed-off-by: Guilherme G. Piccoli <gpiccoli@...ux.vnet.ibm.com>

Good catch, and you are quite correct, a write barrier orders only
before and after itself, doing nothing to impose order on preceding
writes among themselves.

Applied, thank you!

							Thanx, Paul

> ---
> 
> v2: added Paul in CC.
> 
>  Documentation/memory-barriers.txt | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt
> index b759a60624fd..a4bbbd1b63a0 100644
> --- a/Documentation/memory-barriers.txt
> +++ b/Documentation/memory-barriers.txt
> @@ -383,8 +383,8 @@ Memory barriers come in four basic varieties:
>       to have any effect on loads.
> 
>       A CPU can be viewed as committing a sequence of store operations to the
> -     memory system as time progresses.  All stores before a write barrier will
> -     occur in the sequence _before_ all the stores after the write barrier.
> +     memory system as time progresses.  All stores _before_ a write barrier
> +     will occur _before_ all the stores after the write barrier.
> 
>       [!] Note that write barriers should normally be paired with read or data
>       dependency barriers; see the "SMP barrier pairing" subsection.
> -- 
> 2.14.1
>