linux-kernel - [tip:x86/urgent] perf/x86/msr: Add missing CPU IDs

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Mon, 25 Sep 2017 03:09:18 -0700
From:   tip-bot for Kan Liang <tipbot@...or.com>
To:     linux-tip-commits@...r.kernel.org
Cc:     linux-kernel@...r.kernel.org, hpa@...or.com, tglx@...utronix.de,
        Kan.liang@...el.com, mingo@...nel.org
Subject: [tip:x86/urgent] perf/x86/msr: Add missing CPU IDs

Commit-ID:  1aaccc40a1864053da26605b0297be16dd52641e
Gitweb:     http://git.kernel.org/tip/1aaccc40a1864053da26605b0297be16dd52641e
Author:     Kan Liang <Kan.liang@...el.com>
AuthorDate: Fri, 8 Sep 2017 17:34:48 -0400
Committer:  Thomas Gleixner <tglx@...utronix.de>
CommitDate: Mon, 25 Sep 2017 09:36:17 +0200

perf/x86/msr: Add missing CPU IDs

Goldmont, Glodmont plus and Xeon Phi have MSR_SMI_COUNT as well.

Signed-off-by: Kan Liang <Kan.liang@...el.com>
Signed-off-by: Thomas Gleixner <tglx@...utronix.de>
Cc: ak@...ux.intel.com
Cc: peterz@...radead.org
Cc: piotr.luc@...el.com
Cc: harry.pan@...el.com
Cc: srinivas.pandruvada@...ux.intel.com
Link: http://lkml.kernel.org/r/20170908213449.6224-2-kan.liang@intel.com

---
 arch/x86/events/msr.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c
index 4bb3ec6..0672367 100644
--- a/arch/x86/events/msr.c
+++ b/arch/x86/events/msr.c
@@ -63,6 +63,14 @@ static bool test_intel(int idx)
 	case INTEL_FAM6_ATOM_SILVERMONT1:
 	case INTEL_FAM6_ATOM_SILVERMONT2:
 	case INTEL_FAM6_ATOM_AIRMONT:
+
+	case INTEL_FAM6_ATOM_GOLDMONT:
+	case INTEL_FAM6_ATOM_DENVERTON:
+
+	case INTEL_FAM6_ATOM_GEMINI_LAKE:
+
+	case INTEL_FAM6_XEON_PHI_KNL:
+	case INTEL_FAM6_XEON_PHI_KNM:
 		if (idx == PERF_MSR_SMI)
 			return true;
 		break;