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Message-ID: <4487028.9zWcgLXlOk@phil>
Date: Tue, 26 Sep 2017 16:00:52 +0200
From: Heiko Stuebner <heiko@...ech.de>
To: Nickey Yang <nickey.yang@...k-chips.com>
Cc: mark.yao@...k-chips.com, robh+dt@...nel.org, mark.rutland@....com,
airlied@...ux.ie, linux-kernel@...r.kernel.org,
dri-devel@...ts.freedesktop.org,
linux-rockchip@...ts.infradead.org, seanpaul@...omium.org,
briannorris@...omium.org, hl@...k-chips.com, zyw@...k-chips.com,
bivvy.bi@...k-chips.com, xbl@...k-chips.com
Subject: Re: [PATCH v2 6/8] arm64: dts: rockchip: rk3399: Correct MIPI DPHY PLL clock
Am Dienstag, 26. September 2017, 15:55:21 CEST schrieb Nickey Yang:
> Mipi-dphy's ref_clk connect to clk_dphy_pll inside rk3399.
> clk_24m -> Gate11[14] -> clk_mipidphy_ref -> Gate21[0] -> clk_dphy_pll
> So correct it.
>
> Signed-off-by: Nickey Yang <nickey.yang@...k-chips.com>
I've already applied this patch from the previous version.
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