linux-kernel - RE: [PATCH 04/11] ia64: make dma_cache

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Message-ID: <063D6719AE5E284EB5DD2968C1650D6DD0089626@AcuExch.aculab.com>
Date:   Wed, 4 Oct 2017 08:59:24 +0000
From:   David Laight <David.Laight@...LAB.COM>
To:     'Christoph Hellwig' <hch@....de>,
        "iommu@...ts.linux-foundation.org" <iommu@...ts.linux-foundation.org>
CC:     Chris Zankel <chris@...kel.net>, Michal Simek <monstr@...str.eu>,
        "linux-ia64@...r.kernel.org" <linux-ia64@...r.kernel.org>,
        "linux-mips@...ux-mips.org" <linux-mips@...ux-mips.org>,
        "linux-sh@...r.kernel.org" <linux-sh@...r.kernel.org>,
        "linuxppc-dev@...ts.ozlabs.org" <linuxppc-dev@...ts.ozlabs.org>,
        "linux-xtensa@...ux-xtensa.org" <linux-xtensa@...ux-xtensa.org>,
        "x86@...nel.org" <x86@...nel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        David Howells <dhowells@...hat.com>,
        "Max Filippov" <jcmvbkbc@...il.com>,
        Guan Xuetao <gxt@...c.pku.edu.cn>,
        "Robin Murphy" <robin.murphy@....com>,
        Marek Szyprowski <m.szyprowski@...sung.com>
Subject: RE: [PATCH 04/11] ia64: make dma_cache_sync a no-op

From: Christoph Hellwig
> Sent: 03 October 2017 11:43
>
> ia64 does not implement DMA_ATTR_NON_CONSISTENT allocations, so it doesn't
> make any sense to do any work in dma_cache_sync given that it must be a
> no-op when dma_alloc_attrs returns coherent memory.
> 
> Signed-off-by: Christoph Hellwig <hch@....de>
> ---
>  arch/ia64/include/asm/dma-mapping.h | 5 -----
>  1 file changed, 5 deletions(-)
> 
> diff --git a/arch/ia64/include/asm/dma-mapping.h b/arch/ia64/include/asm/dma-mapping.h
> index 3ce5ab4339f3..99dfc1aa9d3c 100644
> --- a/arch/ia64/include/asm/dma-mapping.h
> +++ b/arch/ia64/include/asm/dma-mapping.h
> @@ -48,11 +48,6 @@ static inline void
>  dma_cache_sync (struct device *dev, void *vaddr, size_t size,
>  	enum dma_data_direction dir)
>  {
> -	/*
> -	 * IA-64 is cache-coherent, so this is mostly a no-op.  However, we do need to
> -	 * ensure that dma_cache_sync() enforces order, hence the mb().
> -	 */
> -	mb();
>  }

Are you sure about this one?
It looks as though you are doing a mechanical change for all architectures.
Some of them are probably stranger than you realise.

Even with cache coherent memory any cpu 'store/write buffer' may not
be snooped by dma reads.

Something needs to flush the store buffer between the last cpu write
to the dma buffer and the write (probably a device register) that
tells the device it can read the memory.

My guess from the comment is that dma_cache_synch() is expected to
include that barrier - and it might not be anywhere else.

	David