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Date:   Sun, 8 Oct 2017 18:06:19 +0530
From:   Anand Moon <linux.amoon@...il.com>
To:     Krzysztof Kozlowski <krzk@...nel.org>
Cc:     Rob Herring <robh+dt@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Russell King <linux@...linux.org.uk>,
        Kukjin Kim <kgene@...nel.org>,
        Kishon Vijay Abraham I <kishon@...com>,
        Bartlomiej Zolnierkiewicz <b.zolnierkie@...sung.com>,
        Lee Jones <lee.jones@...aro.org>,
        Chunfeng Yun <chunfeng.yun@...iatek.com>,
        Vivek Gautam <vivek.gautam@...eaurora.org>,
        Andrzej Pietrasiewicz <andrzej.p@...sung.com>,
        devicetree <devicetree@...r.kernel.org>,
        linux-arm-kernel <linux-arm-kernel@...ts.infradead.org>,
        "linux-samsung-soc@...r.kernel.org" 
        <linux-samsung-soc@...r.kernel.org>,
        Linux Kernel <linux-kernel@...r.kernel.org>
Subject: Re: [RFC 1/2] ARM: dts: exynos: update the usbdrd phy and ref clk

Hi Krzysztof,

On 6 October 2017 at 12:08, Krzysztof Kozlowski <krzk@...nel.org> wrote:
> On Fri, Oct 6, 2017 at 6:36 AM, Anand Moon <linux.amoon@...il.com> wrote:
>> update the usbdrd link control and phy contol clks.
>
> The commit title and especially commit message should explain why you
> are doing this and what are you doing. "Update" is not enough.
> Everything could be called update.
>
> Therefore I do not understand the reason behind the patch.
>
> BR,
> Krzysztof

so as per the driver.
@clk: phy clock for register access
@ref_clk: reference clock to PHY block from which PHY's operational
clocks are derived

Both CLK_SCLK_USBPHY300 and CLK_SCLK_USBD300 belong to FSYS Clock
and CLK_USBD300 clk is being used by the usbdrd dwc3 module.

[0] https://github.com/torvalds/linux/blob/master/drivers/clk/samsung/clk-exynos5420.c#L1040-L1053

So their is mismatch of the clk used by the usbdrd driver.
with the above changes the driver work well with camera and disk drives
connected to usb 3.0 ports and their is improvement in the performance.

root@...oid:~# lsusb -t
/:  Bus 06.Port 1: Dev 1, Class=root_hub, Driver=xhci-hcd/1p, 5000M
/:  Bus 05.Port 1: Dev 1, Class=root_hub, Driver=xhci-hcd/1p, 480M
    |__ Port 1: Dev 3, If 0, Class=Vendor Specific Class, Driver=r8152, 480M
/:  Bus 04.Port 1: Dev 1, Class=root_hub, Driver=xhci-hcd/1p, 5000M
    |__ Port 1: Dev 2, If 0, Class=Hub, Driver=hub/2p, 5000M
        |__ Port 1: Dev 3, If 0, Class=Mass Storage, Driver=uas, 5000M
        |__ Port 2: Dev 4, If 0, Class=Mass Storage, Driver=uas, 5000M
/:  Bus 03.Port 1: Dev 1, Class=root_hub, Driver=xhci-hcd/1p, 480M
    |__ Port 1: Dev 2, If 0, Class=Hub, Driver=hub/2p, 480M
/:  Bus 02.Port 1: Dev 1, Class=root_hub, Driver=exynos-ohci/3p, 12M
/:  Bus 01.Port 1: Dev 1, Class=root_hub, Driver=exynos-ehci/3p, 480M

Best Regards
-Anand

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