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Message-ID: <CAD=FV=VnFyC8Z5iD+HF7OVVAyNjOoAJZKj9SO7jaL8q+0h8qxg@mail.gmail.com>
Date:   Wed, 11 Oct 2017 16:55:31 -0700
From:   Doug Anderson <dianders@...omium.org>
To:     Shawn Lin <shawn.lin@...k-chips.com>
Cc:     Jaehoon Chung <jh80.chung@...sung.com>,
        Ulf Hansson <ulf.hansson@...aro.org>,
        Brian Norris <briannorris@...omium.org>,
        Alexandru M Stan <amstan@...omium.org>,
        Ziyuan Xu <xzy.xu@...k-chips.com>,
        "linux-mmc@...r.kernel.org" <linux-mmc@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Emil Renner Berthing <kernel@...il.dk>
Subject: Re: [PATCH 2/3] mmc: dw_mmc: Fix the CTO timeout calculation

Hi,

On Mon, Oct 9, 2017 at 12:03 AM, Shawn Lin <shawn.lin@...k-chips.com> wrote:
> Hi
>
> On 2017/9/28 4:56, Douglas Anderson wrote:
>>
>> In the commit 03de19212ea3 ("mmc: dw_mmc: introduce timer for broken
>> command transfer over scheme") we tried to calculate the expected
>> hardware command timeout value.  Unfortunately that calculation isn't
>> quite correct in all cases.  It used "bus_hz" but, as far as I can
>> tell, it's supposed to use the card clock.  Let's account for the div
>> value, which is documented as 2x the value stored in the register, or
>> 1 if the register is 0.
>
>
> Good catch.
> Would you mind appending a new patch to fix the drto case?

I can add it to the series.  It'll be a separate patch, though, since
I wouldn't suggest backporting that one.  The DRTO timeout is so long
that it's really hard to hit it in this way so I think the argument is
much more academic there.  Still good to fix it, though.

-Doug

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