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Message-ID: <f18b6a72-e255-9aa4-6ebd-852ce1a27a4e@nvidia.com>
Date: Thu, 12 Oct 2017 09:49:04 +0100
From: Jon Hunter <jonathanh@...dia.com>
To: Dmitry Osipenko <digetx@...il.com>,
Thierry Reding <thierry.reding@...il.com>,
Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Rob Herring <robh+dt@...nel.org>,
Mauro Carvalho Chehab <mchehab@...nel.org>,
Stephen Warren <swarren@...dotorg.org>
CC: Dan Carpenter <dan.carpenter@...cle.com>,
<linux-media@...r.kernel.org>, <linux-tegra@...r.kernel.org>,
<devel@...verdev.osuosl.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v3 2/2] ARM: dts: tegra20: Add video decoder node
On 11/10/17 21:08, Dmitry Osipenko wrote:
> Add a device node for the video decoder engine found on Tegra20.
>
> Signed-off-by: Dmitry Osipenko <digetx@...il.com>
> ---
> arch/arm/boot/dts/tegra20.dtsi | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
>
> diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
> index 7c85f97f72ea..1b5d54b6c0cb 100644
> --- a/arch/arm/boot/dts/tegra20.dtsi
> +++ b/arch/arm/boot/dts/tegra20.dtsi
> @@ -249,6 +249,23 @@
> */
> };
>
> + vde@...1a000 {
> + compatible = "nvidia,tegra20-vde";
> + reg = <0x6001a000 0x3D00 /* VDE registers */
> + 0x40000400 0x3FC00>; /* IRAM region */
> + reg-names = "regs", "iram";
> + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, /* UCQ error interrupt */
> + <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */
> + <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
> + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, /* BSE-A interrupt */
> + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */
> + interrupt-names = "ucq-error", "sync-token", "bsev", "bsea", "sxe";
> + clocks = <&tegra_car TEGRA20_CLK_VDE>;
> + clock-names = "vde";
> + resets = <&tegra_car 61>;
> + reset-names = "vde";
> + };
> +
I don't see any binding documentation for this node. We need to make
sure we add this.
Jon
--
nvpublic
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