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Message-ID: <1507778395.21840.15.camel@mtkswgap22>
Date: Thu, 12 Oct 2017 11:19:55 +0800
From: Sean Wang <sean.wang@...iatek.com>
To: Matthias Brugger <matthias.bgg@...il.com>
CC: <robh+dt@...nel.org>, <mark.rutland@....com>,
<lgirdwood@...il.com>, <broonie@...nel.org>,
<jamesjj.liao@...iatek.com>, <henryc.chen@...iatek.com>,
<devicetree@...r.kernel.org>, <linux-mediatek@...ts.infradead.org>,
<chen.zhong@...iatek.com>, <chenglin.xu@...iatek.com>,
<linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v3 5/9] soc: mediatek: pwrap: add pwrap_write32 for
writing in 32-bit mode
On Tue, 2017-10-10 at 11:38 +0200, Matthias Brugger wrote:
>
> On 08/15/2017 11:09 AM, sean.wang@...iatek.com wrote:
> > From: Sean Wang <sean.wang@...iatek.com>
> >
> > Some regulators such as MediaTek MT6380 also has to be written in
> > 32-bit mode. So the patch adds pwrap_write32, rename old pwrap_write
> > into pwrap_write16 and one additional function pointer is introduced
> > for increasing flexibility allowing the determination which mode is
> > used by the pwrap slave detection through device tree.
> >
> > Signed-off-by: Chenglin Xu <chenglin.xu@...iatek.com>
> > Signed-off-by: Chen Zhong <chen.zhong@...iatek.com>
> > Signed-off-by: Sean Wang <sean.wang@...iatek.com>
> > ---
> > drivers/soc/mediatek/mtk-pmic-wrap.c | 63 +++++++++++++++++++++++++++---------
> > 1 file changed, 47 insertions(+), 16 deletions(-)
> >
> > diff --git a/drivers/soc/mediatek/mtk-pmic-wrap.c b/drivers/soc/mediatek/mtk-pmic-wrap.c
> > index 7cd581b..9d1f4c6 100644
> > --- a/drivers/soc/mediatek/mtk-pmic-wrap.c
> > +++ b/drivers/soc/mediatek/mtk-pmic-wrap.c
> > @@ -506,6 +506,7 @@ struct pwrap_slv_type {
> > * which type is used by the detection through device tree.
> > */
> > int (*pwrap_read)(struct pmic_wrapper *wrp, u32 adr, u32 *rdata);
> > + int (*pwrap_write)(struct pmic_wrapper *wrp, u32 adr, u32 wdata);
> > };
> >
> > struct pmic_wrapper {
> > @@ -600,22 +601,6 @@ static int pwrap_wait_for_state(struct pmic_wrapper *wrp,
> > } while (1);
> > }
> >
> > -static int pwrap_write(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
> > -{
> > - int ret;
> > -
> > - ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
> > - if (ret) {
> > - pwrap_leave_fsm_vldclr(wrp);
> > - return ret;
> > - }
> > -
> > - pwrap_writel(wrp, (1 << 31) | ((adr >> 1) << 16) | wdata,
> > - PWRAP_WACS2_CMD);
> > -
> > - return 0;
> > -}
> > -
> > static int pwrap_read16(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
> > {
> > int ret;
> > @@ -672,6 +657,49 @@ static int pwrap_read(struct pmic_wrapper *wrp, u32 adr, u32 *rdata)
> > return wrp->slave->pwrap_read(wrp, adr, rdata);
> > }
> >
> > +static int pwrap_write16(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
> > +{
> > + int ret;
> > +
> > + ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
> > + if (ret) {
> > + pwrap_leave_fsm_vldclr(wrp);
> > + return ret;
> > + }
> > +
> > + pwrap_writel(wrp, (1 << 31) | ((adr >> 1) << 16) | wdata,
> > + PWRAP_WACS2_CMD);
> > +
> > + return 0;
> > +}
> > +
> > +static int pwrap_write32(struct pmic_wrapper *wrp, u32 adr, u32 wdata)
> > +{
> > + int ret, msb, rdata;
> > +
> > + for (msb = 0; msb < 2; msb++) {
> > + ret = pwrap_wait_for_state(wrp, pwrap_is_fsm_idle);
> > + if (ret) {
> > + pwrap_leave_fsm_vldclr(wrp);
> > + return ret;
> > + }
> > +
> > + pwrap_writel(wrp, (1 << 31) | (msb << 30) | (adr << 16) |
> > + ((wdata >> (msb * 16)) & 0xffff),
> > + PWRAP_WACS2_CMD);
> > +
> > + if (!msb)
> > + pwrap_read(wrp, adr, &rdata);
>
> Just so that I understand, you have to read back the half-written register
> before you can write the second part?
>
Yup, the pwrap_read operation is the requirement of hardware used for
the synchronization between two successive 16-bit pwrap_writel
operations composing one 32-bit bus writing. Otherwise, we'll find the
result fails for the lower 16-bit pwrap writing.
> Other then that it looks fine to me.
>
> Regards,
> Matthias
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