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Date:   Fri, 13 Oct 2017 22:43:02 +0200
From:   Radim Krčmář <rkrcmar@...hat.com>
To:     Wanpeng Li <kernellwp@...il.com>
Cc:     linux-kernel@...r.kernel.org, kvm@...r.kernel.org,
        Paolo Bonzini <pbonzini@...hat.com>,
        Wanpeng Li <wanpeng.li@...mail.com>
Subject: Re: [PATCH] KVM: LAPIC: Level-sensitive interrupts are not support
 for LINT1

2017-10-12 21:27-0700, Wanpeng Li:
> From: Wanpeng Li <wanpeng.li@...mail.com>
> 
> SDM 10.5.1 mentioned:
>  Software should always set the trigger mode in the LVT LINT1 register to 0 (edge
>  sensitive). Level-sensitive interrupts are not supported from LINT1.
> 
> I can intercept both Linux/windows 7/windows 2016 guests on my hand will set 
> Level-sensitive trigger mode to LVT LINT1 register during boot.  

And there is no problem with that, software can do that, delivery
through LINT1 is just undefined with that (most likely behaviors are:
deliver as edge and don't deliver.).

> This patch avoids the software too fool to set the level-sensitive trigger mode 
> to LVT LINT1 register.

The software should see the value it writes, though, so the current
behavior is better.

Do we hit a KVM bug if the software uses APIC_LVT_LEVEL_TRIGGER?

Thanks.

> Cc: Paolo Bonzini <pbonzini@...hat.com>
> Cc: Radim Krčmář <rkrcmar@...hat.com>
> Signed-off-by: Wanpeng Li <wanpeng.li@...mail.com>
> ---
>  arch/x86/kvm/lapic.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
> index a778f1a..26593c7 100644
> --- a/arch/x86/kvm/lapic.c
> +++ b/arch/x86/kvm/lapic.c
> @@ -1758,6 +1758,8 @@ int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
>  			val |= APIC_LVT_MASKED;
>  
>  		val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
> +		if (reg == APIC_LVT1)
> +			val &= ~APIC_LVT_LEVEL_TRIGGER;
>  		kvm_lapic_set_reg(apic, reg, val);
>  
>  		break;
> -- 
> 2.7.4
> 

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