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Date:   Mon, 16 Oct 2017 11:55:40 +0300
From:   "Kirill A. Shutemov" <kirill@...temov.name>
To:     Brian Gerst <brgerst@...il.com>
Cc:     "Kirill A. Shutemov" <kirill.shutemov@...ux.intel.com>,
        Ingo Molnar <mingo@...hat.com>,
        Linus Torvalds <torvalds@...ux-foundation.org>,
        the arch/x86 maintainers <x86@...nel.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        "H. Peter Anvin" <hpa@...or.com>,
        Andy Lutomirski <luto@...capital.net>,
        Cyrill Gorcunov <gorcunov@...nvz.org>,
        Borislav Petkov <bp@...e.de>, Andi Kleen <ak@...ux.intel.com>,
        Linux-MM <linux-mm@...ck.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>
Subject: Re: [PATCHv2, RFC] x86/boot/compressed/64: Handle 5-level paging
 boot if kernel is above 4G

On Sat, Oct 14, 2017 at 01:19:08PM -0400, Brian Gerst wrote:
> From what we've seen with the TLB flush rework, having potential
> garbage in the page tables that speculative reads can see can cause
> bad things like machine checks.  It would be best to have a second
> temporary page just for the page table (and properly cleared).

Hm. Interesting. Is there a place where I can read more about this?

> The trampoline also needs its own stack, in case the stack pointer was
> above 4G.

You are right, we need new stack. I've missed that.

> That could be at the end of the code page, since you only need 8 bytes.

When I wrote about 8 bytes, I referred the usage of page table, not code.
We use more than 8 bytes of code, but this should enough in the page.

-- 
 Kirill A. Shutemov

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