linux-kernel - Re: [PATCH v5 4/6] perf: hisi: Add support for HiSilicon SoC HHA PMU driver

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20171017151826.acumob5ldoueiyg6@lakrids.cambridge.arm.com>
Date:   Tue, 17 Oct 2017 16:18:26 +0100
From:   Mark Rutland <mark.rutland@....com>
To:     Shaokun Zhang <zhangshaokun@...ilicon.com>
Cc:     will.deacon@....com, jonathan.cameron@...wei.com,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        linux-doc@...r.kernel.org, linuxarm@...wei.com,
        Anurup M <anurup.m@...wei.com>
Subject: Re: [PATCH v5 4/6] perf: hisi: Add support for HiSilicon SoC HHA PMU
 driver

On Tue, Aug 22, 2017 at 04:07:55PM +0800, Shaokun Zhang wrote:
> L3 cache coherence is maintained by Hydra Home Agent (HHA) in HiSilicon
> SoC. This patch adds support for HHA PMU driver, Each HHA has own
> control, counter and interrupt registers and is an separate PMU. For
> each HHA PMU, it has 16-programable counters and each counter is
> free-running. Interrupt is supported to handle counter (48-bits)
> overflow.

My comments here are the same as for the L3C PMU driver.

Thanks,
Mark.