linux-kernel - [PATCH V2 3/3] RDMA/hns: Update the PD&CQE&MTT specification in hip08

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Message-ID: <1508319166-116987-4-git-send-email-xavier.huwei@huawei.com>
Date:   Wed, 18 Oct 2017 17:32:46 +0800
From:   "Wei Hu (Xavier)" <xavier.huwei@...wei.com>
To:     <dledford@...hat.com>, <leon@...nel.org>
CC:     <linux-rdma@...r.kernel.org>, <xavier.huwei@...wei.com>,
        <lijun_nudt@....com>, <oulijun@...wei.com>,
        <charles.chenxin@...wei.com>, <liuyixian@...wei.com>,
        <zhangxiping3@...wei.com>, <linuxarm@...wei.com>,
        <linux-kernel@...r.kernel.org>, <shaobohsu@....com>,
        <shaoboxu@....com>, <shaobo.xu@...el.com>
Subject: [PATCH V2 3/3] RDMA/hns: Update the PD&CQE&MTT specification in hip08

This patch updates the PD specification to 16M for hip08. And it
updates the numbers of mtt and cqe segments for the buddy.

As the CQE supports hop num 1 addressing, the CQE specification is
64k. This patch updates to set the CQE specification to 64k.

Signed-off-by: Shaobo Xu <xushaobo2@...wei.com>
Signed-off-by: Wei Hu (Xavier) <xavier.huwei@...wei.com>
Signed-off-by: Lijun Ou <oulijun@...wei.com>
---
 drivers/infiniband/hw/hns/hns_roce_hw_v2.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h
index 65ed3f8..6106ad1 100644
--- a/drivers/infiniband/hw/hns/hns_roce_hw_v2.h
+++ b/drivers/infiniband/hw/hns/hns_roce_hw_v2.h
@@ -47,16 +47,16 @@
 #define HNS_ROCE_V2_MAX_QP_NUM			0x2000
 #define HNS_ROCE_V2_MAX_WQE_NUM			0x8000
 #define HNS_ROCE_V2_MAX_CQ_NUM			0x8000
-#define HNS_ROCE_V2_MAX_CQE_NUM			0x400000
+#define HNS_ROCE_V2_MAX_CQE_NUM			0x10000
 #define HNS_ROCE_V2_MAX_RQ_SGE_NUM		0x100
 #define HNS_ROCE_V2_MAX_SQ_SGE_NUM		0xff
 #define HNS_ROCE_V2_MAX_SQ_INLINE		0x20
 #define HNS_ROCE_V2_UAR_NUM			256
 #define HNS_ROCE_V2_PHY_UAR_NUM			1
 #define HNS_ROCE_V2_MAX_MTPT_NUM		0x8000
-#define HNS_ROCE_V2_MAX_MTT_SEGS		0x100000
-#define HNS_ROCE_V2_MAX_CQE_SEGS		0x10000
-#define HNS_ROCE_V2_MAX_PD_NUM			0x400000
+#define HNS_ROCE_V2_MAX_MTT_SEGS		0x1000000
+#define HNS_ROCE_V2_MAX_CQE_SEGS		0x1000000
+#define HNS_ROCE_V2_MAX_PD_NUM			0x1000000
 #define HNS_ROCE_V2_MAX_QP_INIT_RDMA		128
 #define HNS_ROCE_V2_MAX_QP_DEST_RDMA		128
 #define HNS_ROCE_V2_MAX_SQ_DESC_SZ		64
-- 
1.9.1