linux-kernel - Re: [PATCH v5 4/6] perf: hisi: Add support for HiSilicon SoC HHA PMU driver

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Message-ID: <4b1620c9-ad8d-63ed-acf1-19ed31643178@hisilicon.com>
Date:   Wed, 18 Oct 2017 21:35:51 +0800
From:   Zhangshaokun <zhangshaokun@...ilicon.com>
To:     Mark Rutland <mark.rutland@....com>
CC:     <will.deacon@....com>, <jonathan.cameron@...wei.com>,
        <linux-arm-kernel@...ts.infradead.org>,
        <linux-kernel@...r.kernel.org>, <linux-doc@...r.kernel.org>,
        <linuxarm@...wei.com>, Anurup M <anurup.m@...wei.com>
Subject: Re: [PATCH v5 4/6] perf: hisi: Add support for HiSilicon SoC HHA PMU
 driver

Hi Mark,

On 2017/10/17 23:18, Mark Rutland wrote:
> On Tue, Aug 22, 2017 at 04:07:55PM +0800, Shaokun Zhang wrote:
>> L3 cache coherence is maintained by Hydra Home Agent (HHA) in HiSilicon
>> SoC. This patch adds support for HHA PMU driver, Each HHA has own
>> control, counter and interrupt registers and is an separate PMU. For
>> each HHA PMU, it has 16-programable counters and each counter is
>> free-running. Interrupt is supported to handle counter (48-bits)
>> overflow.
> 
> My comments here are the same as for the L3C PMU driver.
> 

Sure.

Thanks,
Shaokun

> Thanks,
> Mark.
> 
> .
>