linux-kernel - Re: [PATCH] KVM: X86: #GP when guest attempts to write MCi banks w/o 0

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Message-ID: <CALMp9eQhDFH_eygVr50r8pCaCuVVbVpz4TyAy3WDY2F_JpM0Hw@mail.gmail.com>
Date:   Wed, 18 Oct 2017 09:28:09 -0700
From:   Jim Mattson <jmattson@...gle.com>
To:     Wanpeng Li <kernellwp@...il.com>
Cc:     LKML <linux-kernel@...r.kernel.org>,
        kvm list <kvm@...r.kernel.org>,
        Paolo Bonzini <pbonzini@...hat.com>,
        Radim Krčmář <rkrcmar@...hat.com>,
        Wanpeng Li <wanpeng.li@...mail.com>
Subject: Re: [PATCH] KVM: X86: #GP when guest attempts to write MCi banks w/o 0

The AMD APM says, "For each error-reporting register bank, software
should set the enable bits to 1 in the MCi_CTL register for the error
types it wants the processor to report. Software can write each
MCi_CTL with all 1s to enable all error-reporting mechanisms.' It does
not say that only all 1's or all 0's are allowed, and it implies that
any value is allowed.

Since this is a vendor-agnostic function, the Intel-specific
constraints should only be applied when virtualizing Intel CPUs (in
particular, Intel P6 family CPUs). The same comment applies to the
existing constraints from commit 890ca9aefa78 ("KVM: Add MCE
support"), which were only partially relaxed by commit 114be429c8cd4
("KVM: allow bit 10 to be cleared in MSR_IA32_MC4_CTL").

On Wed, Oct 18, 2017 at 2:49 AM, Wanpeng Li <kernellwp@...il.com> wrote:
> From: Wanpeng Li <wanpeng.li@...mail.com>
>
> SDM section 15.3.2.2~15.3.2.4 mentioned that MCi_STATUS/ADDR/MISC, when the
> registers are implemented, these registers can be cleared by explicitly writing
> 0s to these registers. Writing 1s to these registers will cause a
> general-protection exception.
>
> The mce is emulated in qemu, so just the guest attempts to write 1 to these
> registers should cause a #GP, this patch does it.
>
> Cc: Radim Krčmář <rkrcmar@...hat.com>
> Cc: Jim Mattson <jmattson@...gle.com>
> Signed-off-by: Wanpeng Li <wanpeng.li@...mail.com>
> ---
>  arch/x86/kvm/x86.c | 9 +++++++--
>  1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
> index 5669af0..a8680ea 100644
> --- a/arch/x86/kvm/x86.c
> +++ b/arch/x86/kvm/x86.c
> @@ -2006,10 +2006,12 @@ static void kvmclock_sync_fn(struct work_struct *work)
>                                         KVMCLOCK_SYNC_PERIOD);
>  }
>
> -static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
> +static int set_msr_mce(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
>  {
>         u64 mcg_cap = vcpu->arch.mcg_cap;
>         unsigned bank_num = mcg_cap & 0xff;
> +       u32 msr = msr_info->index;
> +       u64 data = msr_info->data;
>
>         switch (msr) {
>         case MSR_IA32_MCG_STATUS:
> @@ -2034,6 +2036,9 @@ static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
>                         if ((offset & 0x3) == 0 &&
>                             data != 0 && (data | (1 << 10)) != ~(u64)0)
>                                 return -1;
> +                       if (!msr_info->host_initiated &&
> +                               (offset & 0x3) != 0 && data != 0)
> +                               return -1;
>                         vcpu->arch.mce_banks[offset] = data;
>                         break;
>                 }
> @@ -2283,7 +2288,7 @@ int kvm_set_msr_common(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
>         case MSR_IA32_MCG_CTL:
>         case MSR_IA32_MCG_STATUS:
>         case MSR_IA32_MC0_CTL ... MSR_IA32_MCx_CTL(KVM_MAX_MCE_BANKS) - 1:
> -               return set_msr_mce(vcpu, msr, data);
> +               return set_msr_mce(vcpu, msr_info);
>
>         case MSR_K7_PERFCTR0 ... MSR_K7_PERFCTR3:
>         case MSR_P6_PERFCTR0 ... MSR_P6_PERFCTR1:
> --
> 2.7.4
>