linux-kernel - Re: [PATCH v4 0/2] irqchip: meson: add support for the gpio interrupt controller

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <87shegieqv.fsf@on-the-bus.cambridge.arm.com>
Date:   Wed, 18 Oct 2017 17:48:24 +0100
From:   Marc Zyngier <marc.zyngier@....com>
To:     Jerome Brunet <jbrunet@...libre.com>
Cc:     Thomas Gleixner <tglx@...utronix.de>,
        Jason Cooper <jason@...edaemon.net>,
        Heiner Kallweit <hkallweit1@...il.com>,
        Kevin Hilman <khilman@...libre.com>,
        Carlo Caione <carlo@...one.org>,
        linux-amlogic@...ts.infradead.org,
        linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH v4 0/2] irqchip: meson: add support for the gpio interrupt controller

On Mon, Sep 18 2017 at  3:46:07 pm BST, Jerome Brunet <jbrunet@...libre.com> wrote:
> This patch series adds support for the GPIO interrupt controller found on
> Amlogic's meson SoC families.
>
> Unlike what the name suggests, this controller is not part of the SoC
> GPIO subsystem. It is a separate controller which can watch almost all
> gpio pads of the SoC and generate and interrupt from it. "Almost" because
> there are always exceptions and some specific gpios (TEST_N) lack this
> capability.
>
> Hardware wise, the controller is a 256 to 8 router with a filtering block
> to select edge or level input and the polarity of the signal. We can't
> setup the filtring to generate a signal on both the high and low polarity
> so, ATM, IRQ_TYPE_EDGE_BOTH is not supported.
>
> The number of interrupt line routed to the controller depends on the SoC,
> and essentially the total number of GPIO available on the different gpio
> controllers of the SoC.
>
> This series has been tested on Amlogic S905-P200 board with the front
> panel power button. Also tested on the Nanopi-k2 with the ethernet PHY
> interrupt pin.
>
> This work is derived from the previous work of Carlo Caione [1].

Queued for 4.15.

	M.
-- 
Jazz is not dead, it just smell funny.