linux-kernel - [PATCH V2 1/4] perf/x86/intel/uncore: use same idx for clinet IMC uncore events

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Message-Id: <1508432137-3984-1-git-send-email-kan.liang@intel.com>
Date:   Thu, 19 Oct 2017 09:55:34 -0700
From:   kan.liang@...el.com
To:     tglx@...utronix.de, peterz@...radead.org, mingo@...hat.com,
        linux-kernel@...r.kernel.org
Cc:     acme@...nel.org, eranian@...gle.com, ak@...ux.intel.com,
        Kan Liang <Kan.liang@...el.com>
Subject: [PATCH V2 1/4] perf/x86/intel/uncore: use same idx for clinet IMC uncore events

From: Kan Liang <Kan.liang@...el.com>

The clinet IMC uncore is the only one who claims two 'fixed counters'.
To specially handle it, event->hw.idx >= UNCORE_PMC_IDX_FIXED is used to
check fixed counters in the generic uncore_perf_event_update.
It does not have problem in current code. Because there are no counters
whose idx is larger than fixed counters. However, it will have problem
if new counter type is introduced in generic code. For example,
freerunning counters.

Actually, the 'fixed counters' in the clinet IMC uncore is not
traditional fixed counter. They are freerunning counters, which don't
need the idx to indicate which counter is assigned. They also have same
bits wide. So it's OK to let them use the same idx. event_base is good
enough to select the proper freerunning counter.

There is no traditional fixed counter in clinet IMC uncore. Let them use
the same idx as fixed event for clinet IMC uncore events.

The following patch will remove the special codes in generic
uncore_perf_event_update.

Signed-off-by: Kan Liang <Kan.liang@...el.com>
---

Changes since V1:
 - New file to address check event->hw.idx >= UNCORE_PMC_IDX_FIXED

 arch/x86/events/intel/uncore_snb.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/arch/x86/events/intel/uncore_snb.c b/arch/x86/events/intel/uncore_snb.c
index db1127c..107e772 100644
--- a/arch/x86/events/intel/uncore_snb.c
+++ b/arch/x86/events/intel/uncore_snb.c
@@ -400,6 +400,13 @@ static int snb_uncore_imc_event_init(struct perf_event *event)
 	event->hw.branch_reg.idx = EXTRA_REG_NONE;
 	/*
 	 * check event is known (whitelist, determines counter)
+	 *
+	 * The events and freerunning counters are 1:1 mapped.
+	 * The freerunning counters are always available.
+	 * It doesn't need hw.idx to indicate which counter is assigned.
+	 * There is no traditional fixed counter support for client IMC.
+	 * So let them reuse the same idx as fixed event.
+	 * Base will be used to get the proper freerunning counter.
 	 */
 	switch (cfg) {
 	case SNB_UNCORE_PCI_IMC_DATA_READS:
@@ -408,7 +415,7 @@ static int snb_uncore_imc_event_init(struct perf_event *event)
 		break;
 	case SNB_UNCORE_PCI_IMC_DATA_WRITES:
 		base = SNB_UNCORE_PCI_IMC_DATA_WRITES_BASE;
-		idx = UNCORE_PMC_IDX_FIXED + 1;
+		idx = UNCORE_PMC_IDX_FIXED;
 		break;
 	default:
 		return -EINVAL;
-- 
2.7.4