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Message-ID: <D692A598-D2C7-433A-84E6-D310299935CC@zytor.com>
Date: Tue, 24 Oct 2017 13:32:51 +0200
From: hpa@...or.com
To: "Kirill A. Shutemov" <kirill@...temov.name>,
Ingo Molnar <mingo@...hat.com>
CC: "Kirill A. Shutemov" <kirill.shutemov@...ux.intel.com>,
Linus Torvalds <torvalds@...ux-foundation.org>, x86@...nel.org,
Thomas Gleixner <tglx@...utronix.de>,
Andrew Morton <akpm@...ux-foundation.org>,
Andy Lutomirski <luto@...capital.net>,
Cyrill Gorcunov <gorcunov@...nvz.org>,
Borislav Petkov <bp@...e.de>, linux-mm@...ck.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH 0/6] Boot-time switching between 4- and 5-level paging for 4.15, Part 1
On October 17, 2017 5:42:41 PM GMT+02:00, "Kirill A. Shutemov" <kirill@...temov.name> wrote:
>On Tue, Oct 03, 2017 at 11:27:54AM +0300, Kirill A. Shutemov wrote:
>> On Fri, Sep 29, 2017 at 05:08:15PM +0300, Kirill A. Shutemov wrote:
>> > The first bunch of patches that prepare kernel to boot-time
>switching
>> > between paging modes.
>> >
>> > Please review and consider applying.
>>
>> Ping?
>
>Ingo, is there anything I can do to get review easier for you?
>
>I hoped to get boot-time switching code into v4.15...
One issue that has come up with this is what happens if the kernel is loaded above 4 GB and we need to switch page table mode. In that case we need enough memory below the 4 GB point to hold a root page table (since we can't write the upper half of cr3 outside of 64-bit mode) and a handful of instructions.
We have no real way to know for sure what memory is safe without parsing all the memory maps and map out all the data structures that The bootloader has left for the kernel. I'm thinking that the best way to deal with this is to add an entry in setup_data to provide a pointers, with the kernel header specifying a necessary size and alignment.
--
Sent from my Android device with K-9 Mail. Please excuse my brevity.
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