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Message-ID: <CADRPPNREzRzzW-VRpm6P3y8_sYwvm_c13n6vjgQZP24fxO9uKQ@mail.gmail.com>
Date: Wed, 25 Oct 2017 16:00:36 -0500
From: Li Yang <leoyang.li@....com>
To: SZ Lin <sz.lin@...a.com>, Shawn Guo <shawnguo@...nel.org>
Cc: Minghuan Lian <Minghuan.Lian@....com>,
Zhiqiang Hou <Zhiqiang.Hou@....com>, andy.tang@....com,
yi.sheng.lin@....com, Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Russell King <linux@...linux.org.uk>,
"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS"
<devicetree@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>,
lkml <linux-kernel@...r.kernel.org>
Subject: Re: [RESEND PATCH] ARM: dts: ls1021a: Add support for QSPI with
ls1021a SoC
On Tue, Sep 12, 2017 at 1:49 AM, SZ Lin <sz.lin@...a.com> wrote:
> Add QSPI node support, and this function is disabled by default
> This setting could be overwritten in board-level definitions
Adding Shawn Guo.
>
> Signed-off-by: SZ Lin <sz.lin@...a.com>
Acked-by: Li Yang <leoyang.li@....com>
> ---
> arch/arm/boot/dts/ls1021a.dtsi | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
> index 7bb9df2c1460..9da876e47810 100644
> --- a/arch/arm/boot/dts/ls1021a.dtsi
> +++ b/arch/arm/boot/dts/ls1021a.dtsi
> @@ -154,6 +154,20 @@
> big-endian;
> };
>
> + qspi: quadspi@...0000 {
> + compatible = "fsl,ls1021a-qspi";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x0 0x1550000 0x0 0x10000>,
> + <0x0 0x40000000 0x0 0x40000000>;
> + reg-names = "QuadSPI", "QuadSPI-memory";
> + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
> + clock-names = "qspi_en", "qspi";
> + clocks = <&clockgen 4 1>, <&clockgen 4 1>;
> + big-endian;
> + status = "disabled";
> + };
> +
> esdhc: esdhc@...0000 {
> compatible = "fsl,esdhc";
> reg = <0x0 0x1560000 0x0 0x10000>;
> --
> 2.14.1
>
> --
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