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Message-ID: <ae561709-4d1a-175a-7801-e8e1524243bd@oracle.com>
Date:   Fri, 27 Oct 2017 18:33:44 -0400
From:   Boris Ostrovsky <boris.ostrovsky@...cle.com>
To:     Juergen Gross <jgross@...e.com>, linux-kernel@...r.kernel.org,
        xen-devel@...ts.xenproject.org, x86@...nel.org
Cc:     hpa@...or.com, tglx@...utronix.de, mingo@...hat.com
Subject: Re: [PATCH v2] xen: support 52 bit physical addresses in pv guests



On 10/27/2017 01:49 PM, Juergen Gross wrote:
> Physical addresses on processors supporting 5 level paging can be up to
> 52 bits wide. For a Xen pv guest running on such a machine those
> physical addresses have to be supported in order to be able to use any
> memory on the machine even if the guest itself does not support 5 level
> paging.
> 
> So when reading/writing a MFN from/to a pte don't use the kernel's
> PTE_PFN_MASK but a new XEN_PTE_MFN_MASK allowing full 40 bit wide MFNs.
> 
> Signed-off-by: Juergen Gross <jgross@...e.com>

Reviewed-by: Boris Ostrovsky <boris.ostrovsky@...cle.com>

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