linux-kernel - Re: [PATCH v3 05/13] irqchip: add initial support for ompic

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Date:   Thu, 26 Oct 2017 22:19:50 -0500
From:   Rob Herring <robh@...nel.org>
To:     Stafford Horne <shorne@...il.com>
Cc:     LKML <linux-kernel@...r.kernel.org>,
        Openrisc <openrisc@...ts.librecores.org>,
        Stefan Kristiansson <stefan.kristiansson@...nalahti.fi>,
        Marc Zyngier <marc.zyngier@....com>,
        Thomas Gleixner <tglx@...utronix.de>,
        Jason Cooper <jason@...edaemon.net>,
        Mark Rutland <mark.rutland@....com>,
        Jonas Bonn <jonas@...thpole.se>,
        "David S. Miller" <davem@...emloft.net>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Mauro Carvalho Chehab <mchehab@...nel.org>,
        Randy Dunlap <rdunlap@...radead.org>,
        devicetree@...r.kernel.org
Subject: Re: [PATCH v3 05/13] irqchip: add initial support for ompic

On Sun, Oct 22, 2017 at 12:15:52PM +0900, Stafford Horne wrote:
> From: Stefan Kristiansson <stefan.kristiansson@...nalahti.fi>
> 
> IPI driver for the Open Multi-Processor Interrupt Controller (ompic) as
> described in the Multi-core support section of the OpenRISC 1.2
> proposed architecture specification:
> 
>   https://github.com/stffrdhrn/doc/raw/arch-1.2-proposal/openrisc-arch-1.2-rev0.pdf
> 
> Each OpenRISC core contains a full interrupt controller which is used in
> the SMP architecture for interrupt balancing.  This IPI device, the
> ompic, is the only external device required for enabling SMP on
> OpenRISC.
> 
> Pending ops are stored in a memory bit mask which can allow multiple
> pending operations to be set and serviced at a time. This is mostly
> borrowed from the alpha IPI implementation.
> 
> Cc: Marc Zyngier <marc.zyngier@....com>
> Cc: Rob Herring <robh@...nel.org>
> Signed-off-by: Stefan Kristiansson <stefan.kristiansson@...nalahti.fi>
> [shorne@...il.com: converted ops to bitmask, wrote commit message]
> Signed-off-by: Stafford Horne <shorne@...il.com>
> ---
> 
> Changes since v2
>  - Fixed some issues with missing static
>  - Fixed spelling issue with multi-core
>  - Added back #interrupt-cells
> 
> Changes since v1
>  - Added openrisc, prefix
>  - Clarified 8 bytes per cpu
>  - Removed #interrupt-cells as this will not be an irq parent
>  - Changed ops to be percpu
>  - Added DTS and intialization failure validations
> 
> 
>  .../interrupt-controller/openrisc,ompic.txt        |  22 +++

Acked-by: Rob Herring <robh@...nel.org>

>  MAINTAINERS                                        |   1 +
>  arch/openrisc/Kconfig                              |   1 +
>  drivers/irqchip/Kconfig                            |   3 +
>  drivers/irqchip/Makefile                           |   1 +
>  drivers/irqchip/irq-ompic.c                        | 205 +++++++++++++++++++++
>  6 files changed, 233 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/openrisc,ompic.txt
>  create mode 100644 drivers/irqchip/irq-ompic.c