linux-kernel - Re: [PATCH v4 05/13] irqchip: add initial support for ompic

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <86mv4974ht.fsf@arm.com>
Date:   Mon, 30 Oct 2017 02:29:18 +0000
From:   Marc Zyngier <marc.zyngier@....com>
To:     Stafford Horne <shorne@...il.com>
Cc:     LKML <linux-kernel@...r.kernel.org>,
        Stefan Kristiansson <stefan.kristiansson@...nalahti.fi>,
        Thomas Gleixner <tglx@...utronix.de>,
        Jason Cooper <jason@...edaemon.net>,
        Rob Herring <robh+dt@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Jonas Bonn <jonas@...thpole.se>,
        "David S. Miller" <davem@...emloft.net>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Mauro Carvalho Chehab <mchehab@...nel.org>,
        Randy Dunlap <rdunlap@...radead.org>,
        devicetree@...r.kernel.org, openrisc@...ts.librecores.org
Subject: Re: [PATCH v4 05/13] irqchip: add initial support for ompic

On Mon, Oct 30 2017 at  8:11:15 am GMT, Stafford Horne <shorne@...il.com> wrote:
> From: Stefan Kristiansson <stefan.kristiansson@...nalahti.fi>
>
> IPI driver for the Open Multi-Processor Interrupt Controller (ompic) as
> described in the Multi-core support section of the OpenRISC 1.2
> architecture specification:
>
>   https://github.com/openrisc/doc/raw/master/openrisc-arch-1.2-rev0.pdf
>
> Each OpenRISC core contains a full interrupt controller which is used in
> the SMP architecture for interrupt balancing.  This IPI device, the
> ompic, is the only external device required for enabling SMP on
> OpenRISC.
>
> Pending ops are stored in a memory bit mask which can allow multiple
> pending operations to be set and serviced at a time. This is mostly
> borrowed from the alpha IPI implementation.
>
> Cc: Marc Zyngier <marc.zyngier@....com>
> Acked-by: Rob Herring <robh@...nel.org>
> Signed-off-by: Stefan Kristiansson <stefan.kristiansson@...nalahti.fi>
> [shorne@...il.com: converted ops to bitmask, wrote commit message]
> Signed-off-by: Stafford Horne <shorne@...il.com>

Reviewed-by: Marc Zyngier <marc.zyngier@....com>

Side question: what is your merge strategy for this? I can take it
through the irqchip tree as it is standalone, but I'm open to other
suggestions.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny.