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Date: Mon, 30 Oct 2017 13:42:16 +0100 From: Niklas Cassel <niklas.cassel@...s.com> To: Niklas Cassel <niklass@...s.com>, Jesper Nilsson <jespern@...s.com>, Bjorn Helgaas <bhelgaas@...gle.com>, Rob Herring <robh+dt@...nel.org>, Mark Rutland <mark.rutland@....com> Cc: linux-arm-kernel@...s.com, linux-pci@...r.kernel.org, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org Subject: [PATCH v2 13/17] bindings: PCI: artpec: Add support for endpoint mode Signed-off-by: Niklas Cassel <niklas.cassel@...s.com> Acked-by: Rob Herring <robh@...nel.org> --- V2: * Split out the DT binding change to a self contained patch. * Added Rob's ack (from V1). No change to this file since V1. Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt b/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt index 4e4aee4439ea..33eef7ae5a23 100644 --- a/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt +++ b/Documentation/devicetree/bindings/pci/axis,artpec6-pcie.txt @@ -4,7 +4,8 @@ This PCIe host controller is based on the Synopsys DesignWare PCIe IP and thus inherits all the common properties defined in designware-pcie.txt. Required properties: -- compatible: "axis,artpec6-pcie", "snps,dw-pcie" +- compatible: "axis,artpec6-pcie", "snps,dw-pcie" for ARTPEC-6 in RC mode; + "axis,artpec6-pcie-ep", "snps,dw-pcie" for ARTPEC-6 in EP mode; - reg: base addresses and lengths of the PCIe controller (DBI), the PHY controller, and configuration address space. - reg-names: Must include the following entries: -- 2.14.2
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