linux-kernel - Re: [PATCH 05/23] x86, mm: document X86_CR4

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Message-ID: <CAGXu5jK=OiZ0mf1DsEaEmdFT+u+v3JHW6OcS=bCc=tx6XW93BA@mail.gmail.com>
Date:   Tue, 31 Oct 2017 16:31:43 -0700
From:   Kees Cook <keescook@...gle.com>
To:     Dave Hansen <dave.hansen@...ux.intel.com>
Cc:     LKML <linux-kernel@...r.kernel.org>, Linux-MM <linux-mm@...ck.org>,
        moritz.lipp@...k.tugraz.at, daniel.gruss@...k.tugraz.at,
        michael.schwarz@...k.tugraz.at, Andy Lutomirski <luto@...nel.org>,
        Linus Torvalds <torvalds@...ux-foundation.org>,
        Hugh Dickins <hughd@...gle.com>, x86@...nel.org
Subject: Re: [PATCH 05/23] x86, mm: document X86_CR4_PGE toggling behavior

On Tue, Oct 31, 2017 at 3:31 PM, Dave Hansen
<dave.hansen@...ux.intel.com> wrote:
>
> The comment says it all here.  The problem here is that the
> X86_CR4_PGE bit affects all PCIDs in a way that is totally
> obscure.
>
> This makes it easier for someone to find if grepping for PCID-
> related stuff and documents the hardware behavior that we are
> depending on.
>
> Signed-off-by: Dave Hansen <dave.hansen@...ux.intel.com>
> Cc: Moritz Lipp <moritz.lipp@...k.tugraz.at>
> Cc: Daniel Gruss <daniel.gruss@...k.tugraz.at>
> Cc: Michael Schwarz <michael.schwarz@...k.tugraz.at>
> Cc: Andy Lutomirski <luto@...nel.org>
> Cc: Linus Torvalds <torvalds@...ux-foundation.org>
> Cc: Kees Cook <keescook@...gle.com>
> Cc: Hugh Dickins <hughd@...gle.com>
> Cc: x86@...nel.org
> ---
>
>  b/arch/x86/include/asm/tlbflush.h |    6 ++++--
>  1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff -puN arch/x86/include/asm/tlbflush.h~kaiser-prep-document-cr4-pge-behavior arch/x86/include/asm/tlbflush.h
> --- a/arch/x86/include/asm/tlbflush.h~kaiser-prep-document-cr4-pge-behavior     2017-10-31 15:03:50.479119470 -0700
> +++ b/arch/x86/include/asm/tlbflush.h   2017-10-31 15:03:50.482119612 -0700
> @@ -258,9 +258,11 @@ static inline void __native_flush_tlb_gl
>         WARN_ON_ONCE(!(cr4 & X86_CR4_PGE));
>         /*
>          * Architecturally, any _change_ to X86_CR4_PGE will fully flush the
> -        * TLB of all entries including all entries in all PCIDs and all
> -        * global pages.  Make sure that we _change_ the bit, regardless of
> +        * all entries.  Make sure that we _change_ the bit, regardless of

nit: "... flush the all entries." Drop "the" in the line above?

>          * whether we had X86_CR4_PGE set in the first place.
> +        *
> +        * Note that just toggling PGE *also* flushes all entries from all
> +        * PCIDs, regardless of the state of X86_CR4_PCIDE.
>          */
>         native_write_cr4(cr4 ^ X86_CR4_PGE);
>         /* Put original CR3 value back: */

pre-existing nit: s/CR3/CR4/

-Kees

-- 
Kees Cook
Pixel Security