linux-kernel - Re: [PATCH] ahci: Add support for Cavium's fifth generation SATA controller

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Message-ID: <dec0ba95-6149-a432-b29a-2d62dd1c3b83@jonmasters.org>
Date:   Tue, 31 Oct 2017 06:05:15 -0400
From:   Jon Masters <jcm@...masters.org>
To:     Christoph Hellwig <hch@...radead.org>,
        Radha Mohan Chintakuntla <mohun106@...il.com>
Cc:     tj@...nel.org, linux-ide@...r.kernel.org,
        linux-kernel@...r.kernel.org,
        Radha Mohan Chintakuntla <rchintakuntla@...ium.com>
Subject: Re: [PATCH] ahci: Add support for Cavium's fifth generation SATA
 controller

On 10/17/2017 02:58 AM, Christoph Hellwig wrote:
> On Tue, Oct 10, 2017 at 10:37:51PM -0700, Radha Mohan Chintakuntla wrote:
>> From: Radha Mohan Chintakuntla <rchintakuntla@...ium.com>
>>
>> This patch adds support for Cavium's fifth generation SATA controller.
>> It is an on-chip controller and complies with AHCI 1.3.1. As the
>> controller uses 64-bit addresses it cannot use the standard AHCI BAR5
>> and so uses BAR4.
> 
> Looks like it isn't actually AHCI 1.3.1 compliant after all then :)

I've asked various folks to followup with Intel to see if the AHCI
specification can be fixed to handle the case in which a 64-bit ABAR is
required. That should be something they'd be interested in for x86 too.

Jon.