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Message-ID: <CALCETrUVC4KMPLNzs1mH=sGs9W9-HtajHAHOtOv0-LaT6uNb+g@mail.gmail.com>
Date:   Wed, 1 Nov 2017 01:03:45 -0700
From:   Andy Lutomirski <luto@...nel.org>
To:     Dave Hansen <dave.hansen@...ux.intel.com>
Cc:     "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "linux-mm@...ck.org" <linux-mm@...ck.org>,
        moritz.lipp@...k.tugraz.at, daniel.gruss@...k.tugraz.at,
        michael.schwarz@...k.tugraz.at,
        Andrew Lutomirski <luto@...nel.org>,
        Linus Torvalds <torvalds@...ux-foundation.org>,
        Kees Cook <keescook@...gle.com>,
        Hugh Dickins <hughd@...gle.com>, X86 ML <x86@...nel.org>
Subject: Re: [PATCH 21/23] x86, pcid, kaiser: allow flushing for future ASID switches

On Tue, Oct 31, 2017 at 3:32 PM, Dave Hansen
<dave.hansen@...ux.intel.com> wrote:
>
> If we change the page tables in such a way that we need an
> invalidation of all contexts (aka. PCIDs / ASIDs) we can
> actively invalidate them by:
>  1. INVPCID for each PCID (works for single pages too).
>  2. Load CR3 with each PCID without the NOFLUSH bit set
>  3. Load CR3 with the NOFLUSH bit set for each and do
>     INVLPG for each address.
>
> But, none of these are really feasible since we have ~6 ASIDs (12 with
> KAISER) at the time that we need to do an invalidation.  So, we just
> invalidate the *current* context and then mark the cpu_tlbstate
> _quickly_.
>
> Then, at the next context-switch, we notice that we had
> 'all_other_ctxs_invalid' marked, and go invalidate all of the
> cpu_tlbstate.ctxs[] entries.
>
> This ensures that any futuee context switches will do a full flush
> of the TLB so they pick up the changes.

I'm convuced.  What was wrong with the old code?  I guess I just don't
see what the problem is that is solved by this patch.

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