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Date:   Wed, 01 Nov 2017 11:32:57 +0000
From:   James Morse <james.morse@....com>
To:     Dongjiu Geng <gengdongjiu@...wei.com>
CC:     catalin.marinas@....com, will.deacon@....com, marc.zyngier@....com,
        christoffer.dall@...aro.org, mark.rutland@....com,
        ard.biesheuvel@...aro.org, robin.murphy@....com,
        cov@...eaurora.org, Dave.Martin@....com, suzuki.poulose@....com,
        linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
        kvmarm@...ts.cs.columbia.edu
Subject: Re: [PATCH v1 0/3] manually add Error Synchronization Barrier at
 exception handler entry and exit

Hi Dongjiu Geng,

On 01/11/17 19:14, Dongjiu Geng wrote:
> Some hardware platform can support RAS Extension, but not support IESB,
> such as Huawei's platform, so software need to insert Synchronization Barrier
> operations at exception handler entry.
> 
> This series patches are based on  James's series patches "SError rework +
> RAS&IESB for firmware first support". In Huawei's platform, we do not
> support IESB, so software needs to insert that.

Surely you don't implement it because your CPU doesn't need it. Can
unrecoverable errors really cross an exception without becoming an SError?

The ESB instruction does the barrier, but it also consumes any pending SError.
As it is this series will silently consume-and-discard uncontainable errors.



Thanks,

James


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