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Date: Wed, 1 Nov 2017 14:54:59 +0300 From: "Kirill A. Shutemov" <kirill.shutemov@...ux.intel.com> To: Ingo Molnar <mingo@...hat.com>, Linus Torvalds <torvalds@...ux-foundation.org>, x86@...nel.org, Thomas Gleixner <tglx@...utronix.de>, "H. Peter Anvin" <hpa@...or.com> Cc: Andy Lutomirski <luto@...capital.net>, Cyrill Gorcunov <gorcunov@...nvz.org>, Borislav Petkov <bp@...e.de>, Andi Kleen <ak@...ux.intel.com>, linux-mm@...ck.org, linux-kernel@...r.kernel.org, "Kirill A. Shutemov" <kirill.shutemov@...ux.intel.com> Subject: [PATCH 0/4] x86: 5-level related changes into decompression code Hi Ingo, While we haven't yet closed on how to handle MAX_PHYSMEM_BITS situation, could you look on changes into kernel decompression code? These changes prepare the code to boot-time switching between paging modes and handle booting in 5-level mode when bootloader put kernel image above 4G, but haven't enabled 5-level paging for us. Please review and consider applying. Kirill A. Shutemov (4): x86/boot/compressed/64: Compile pagetable.c unconditionally x86/boot/compressed/64: Detect and handle 5-level paging at boot-time x86/boot/compressed/64: Introduce place_trampoline() x86/boot/compressed/64: Handle 5-level paging boot if kernel is above 4G arch/x86/boot/compressed/Makefile | 2 +- arch/x86/boot/compressed/head_64.S | 99 +++++++++++++++++++++++++----------- arch/x86/boot/compressed/pagetable.c | 66 ++++++++++++++++++++++++ arch/x86/boot/compressed/pagetable.h | 18 +++++++ 4 files changed, 154 insertions(+), 31 deletions(-) create mode 100644 arch/x86/boot/compressed/pagetable.h -- 2.14.2
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