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Date:   Wed, 1 Nov 2017 18:26:34 -0700
From:   David Daney <ddaney@...iumnetworks.com>
To:     Florian Fainelli <f.fainelli@...il.com>,
        David Daney <david.daney@...ium.com>,
        linux-mips@...ux-mips.org, ralf@...ux-mips.org,
        James Hogan <james.hogan@...s.com>, netdev@...r.kernel.org,
        "David S. Miller" <davem@...emloft.net>,
        Rob Herring <robh+dt@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        "Williams, Aaron" <Aaron.Williams@...iumnetworks.com>
Cc:     linux-kernel@...r.kernel.org,
        "Steven J. Hill" <steven.hill@...ium.com>,
        devicetree@...r.kernel.org, Carlos Munoz <cmunoz@...ium.com>
Subject: Re: [PATCH 1/7] dt-bindings: Add Cavium Octeon Common Ethernet
 Interface.

On 11/01/2017 06:09 PM, Florian Fainelli wrote:
> On 11/01/2017 05:36 PM, David Daney wrote:
>> From: Carlos Munoz <cmunoz@...ium.com>
>>
>> Add bindings for Common Ethernet Interface (BGX) block.
>>
>> Signed-off-by: Carlos Munoz <cmunoz@...ium.com>
>> Signed-off-by: Steven J. Hill <Steven.Hill@...ium.com>
>> Signed-off-by: David Daney <david.daney@...ium.com>
>> ---
> [snip]
>> +Properties:
>> +
>> +- compatible: "cavium,octeon-7360-xcv": Compatibility with cn73xx SOCs.
>> +
>> +- reg: The index of the interface within the BGX block.
>> +
>> +- local-mac-address: Mac address for the interface.
>> +
>> +- phy-handle: phandle to the phy node connected to the interface.
>> +
>> +- cavium,rx-clk-delay-bypass: Set to <1> to bypass the rx clock delay setting.
>> +  Needed by the Micrel PHY.
> 
> Is not that implied by an appropriate "phy-mode" property already?

I think you are correct.  That string never appears in the source code, 
so I am going to remove that property from the binding document for the 
next revision of the patch set.

Thanks,
David Daney

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