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Message-ID: <alpine.DEB.2.20.1711021510060.2090@nanos>
Date: Thu, 2 Nov 2017 15:11:01 +0100 (CET)
From: Thomas Gleixner <tglx@...utronix.de>
To: "Liang, Kan" <kan.liang@...el.com>
cc: "peterz@...radead.org" <peterz@...radead.org>,
"mingo@...hat.com" <mingo@...hat.com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"acme@...nel.org" <acme@...nel.org>,
"eranian@...gle.com" <eranian@...gle.com>,
"ak@...ux.intel.com" <ak@...ux.intel.com>
Subject: RE: [PATCH V3 1/5] perf/x86/intel/uncore: customized pmu event read
for client IMC uncore
On Thu, 2 Nov 2017, Liang, Kan wrote:
> > On Thu, 2 Nov 2017, Thomas Gleixner wrote:
> > > On Thu, 2 Nov 2017, Liang, Kan wrote:
> > > > > On Tue, 24 Oct 2017, kan.liang@...el.com wrote:
> > > > > > - if (event->hw.idx >= UNCORE_PMC_IDX_FIXED)
> > > > > > + if (event->hw.idx == UNCORE_PMC_IDX_FIXED)
> > > > > > shift = 64 - uncore_fixed_ctr_bits(box);
> > > > > > else
> > > > > > shift = 64 - uncore_perf_ctr_bits(box); diff --git
> > > > > > a/arch/x86/events/intel/uncore_snb.c
> > > > > > b/arch/x86/events/intel/uncore_snb.c
> > > > > > index db1127c..9d5cd3f 100644
> > > > > > --- a/arch/x86/events/intel/uncore_snb.c
> > > > > > +++ b/arch/x86/events/intel/uncore_snb.c
> > > > > > @@ -498,6 +498,30 @@ static void snb_uncore_imc_event_del(struct
> > > > > perf_event *event, int flags)
> > > > > > snb_uncore_imc_event_stop(event, PERF_EF_UPDATE); }
> > > > > >
> > > > > > +static void snb_uncore_imc_event_read(struct perf_event *event) {
> > > > > > + struct intel_uncore_box *box = uncore_event_to_box(event);
> > > > > > + u64 prev_count, new_count, delta;
> > > > > > + int shift;
> > > > > > +
> > > > > > + if (event->hw.idx >= UNCORE_PMC_IDX_FIXED)
> > > > >
> > > > > And this needs to be >= because?
> > > >
> > > > Patch 5/5 will clean up the client IMC uncore.
> > > > Before that, we still need it to make client IMC uncore work.
> > > >
> > > > This patch isolates the >= case for client IMC uncore.
> > >
> > > Fair enough. A comment to that effect (even when removed later) would
> > > have avoided that question.
> >
> > Thinking more about it. The current code only supports the fixed one, right?
> > So why would it deal with anything > FIXED?
> >
>
> There are two free running counters in IMC.
> To support the second one, the previous code implicitly do
> UNCORE_PMC_IDX_FIXED + 1.
> So it has to deal with > FIXED case.
>
> case SNB_UNCORE_PCI_IMC_DATA_READS:
> base = SNB_UNCORE_PCI_IMC_DATA_READS_BASE;
> idx = UNCORE_PMC_IDX_FIXED;
> break;
> case SNB_UNCORE_PCI_IMC_DATA_WRITES:
> base = SNB_UNCORE_PCI_IMC_DATA_WRITES_BASE;
> idx = UNCORE_PMC_IDX_FIXED + 1;
> break;
> default:
> return -EINVAL;
Fugly that is, but as its cleaned up later....
Thanks,
tglx
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