lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite for Android: free password hash cracker in your pocket
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <7c2c39a3-8b24-e89a-1c67-385a5c6a2976@oracle.com>
Date:   Fri, 3 Nov 2017 10:13:08 -0700
From:   Krish Sadhukhan <krish.sadhukhan@...cle.com>
To:     Wanpeng Li <kernellwp@...il.com>
Cc:     Paolo Bonzini <pbonzini@...hat.com>,
        Radim Krcmar <rkrcmar@...hat.com>, kvm <kvm@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Jim Mattson <jmattson@...gle.com>
Subject: Re: [PATCH v5 2/3] KVM: nVMX: Validate the IA32_BNDCFGS on nested
 VM-entry



On 11/02/2017 11:40 PM, Wanpeng Li wrote:
> 2017-11-03 14:31 GMT+08:00 Krish Sadhukhan <krish.sadhukhan@...cle.com>:
>>
>> On 11/02/2017 05:50 PM, Wanpeng Li wrote:
>>> From: Wanpeng Li <wanpeng.li@...mail.com>
>>>
>>> According to the SDM, if the "load IA32_BNDCFGS" VM-entry controls is 1,
>>> the
>>> following checks are performed on the field for the IA32_BNDCFGS MSR:
>>>    - Bits reserved in the IA32_BNDCFGS MSR must be 0.
>>>    - The linear address in bits 63:12 must be canonical.
>>>
>>> Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@...cle.com>
>>> Cc: Paolo Bonzini <pbonzini@...hat.com>
>>> Cc: Radim Krčmář <rkrcmar@...hat.com>
>>> Cc: Jim Mattson <jmattson@...gle.com>
>>> Signed-off-by: Wanpeng Li <wanpeng.li@...mail.com>
>>> ---
>>> v3 -> v4:
>>>    * simply condition
>>>    * use && instead of nested "if"s
>>>
>>>    arch/x86/kvm/vmx.c | 5 +++++
>>>    1 file changed, 5 insertions(+)
>>>
>>> diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
>>> index e6c8ffa..6cf3972 100644
>>> --- a/arch/x86/kvm/vmx.c
>>> +++ b/arch/x86/kvm/vmx.c
>>> @@ -10805,6 +10805,11 @@ static int check_vmentry_postreqs(struct kvm_vcpu
>>> *vcpu, struct vmcs12 *vmcs12,
>>>                          return 1;
>>>          }
>>>    +     if (kvm_mpx_supported() &&
>>> +               (is_noncanonical_address(vmcs12->guest_bndcfgs &
>>> PAGE_MASK, vcpu) ||
>>> +               (vmcs12->guest_bndcfgs & MSR_IA32_BNDCFGS_RSVD)))
>>> +                       return 1;
>>> +
>>>          return 0;
>>>    }
>>>
>> Hi Wanpeng,
>>    The SDM check is performed only when "load IA32_BNDCFGS" VM-entry control
>> is 1. But vmx_mpx_supported() returns true when both "load IA32_BNDCFGS" and
>> "store IA32_BNDCFGS" VM-entry controls are 1. Therefore your check is
>> performed when both controls are 1. Did I miss something here ?
> https://lkml.org/lkml/2017/11/2/748 Paolo hopes the simplification.
>
> Regards,
> Wanpeng Li
I got that simplification and your changes look good to me.


However, I am still curious know the reason why vmx_mpx_supported() 
returns true only when both controls are true whereas the SDM states the 
following:

    "IA32_BNDCFGS (64 bits). This field is supported only on processors 
that support either the 1-setting of the  “load IA32_BNDCFGS” VM-entry 
control or that of the “clear IA32_BNDCFGS” VM-exit control."

Thanks,
Krish

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ