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Date:   Fri,  3 Nov 2017 12:26:06 -0700
From:   Nitin Gupta <nitin.m.gupta@...cle.com>
To:     "David S. Miller" <davem@...emloft.net>
Cc:     Al Viro <viro@...IV.linux.org.uk>,
        Nitin Gupta <nitin.m.gupta@...cle.com>,
        "David S. Miller" <davem@...emloft.net>,
        "Liam R. Howlett" <Liam.Howlett@...cle.com>,
        Vijay Kumar <vijay.ac.kumar@...cle.com>,
        Bob Picco <bob.picco@...cle.com>,
        Allen Pais <allen.pais@...cle.com>, sparclinux@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: [PATCH] sparc64: Fix page table walk for PUD hugepages

For a PUD hugepage entry, we need to propagate bits [32:22]
from virtual address to resolve at 4M granularity. However,
the current code was incorrectly propagating bits [29:19].
This bug can cause incorrect data to be returned for pages
backed with 16G hugepages.

Signed-off-by: Nitin Gupta <nitin.m.gupta@...cle.com>
Reported-by: Al Viro <viro@...IV.linux.org.uk>
Cc: Al Viro <viro@...IV.linux.org.uk>

diff --git a/arch/sparc/include/asm/tsb.h b/arch/sparc/include/asm/tsb.h
index acf55063aa3d..ca0de1646f1e 100644
--- a/arch/sparc/include/asm/tsb.h
+++ b/arch/sparc/include/asm/tsb.h
@@ -216,7 +216,7 @@ extern struct tsb_phys_patch_entry __tsb_phys_patch, __tsb_phys_patch_end;
 	sllx		REG2, 32, REG2;			\
 	andcc		REG1, REG2, %g0;		\
 	be,pt		%xcc, 700f;			\
-	 sethi		%hi(0x1ffc0000), REG2;		\
+	 sethi		%hi(0xffe00000), REG2;		\
 	sllx		REG2, 1, REG2;			\
 	brgez,pn	REG1, FAIL_LABEL;		\
 	 andn		REG1, REG2, REG1;		\
-- 
2.13.1

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