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Message-ID: <20171103050442.GJ29237@lianli.shorne-pla.net>
Date:   Fri, 3 Nov 2017 14:04:42 +0900
From:   Stafford Horne <shorne@...il.com>
To:     LKML <linux-kernel@...r.kernel.org>
Cc:     Openrisc <openrisc@...ts.librecores.org>,
        Rob Herring <robh+dt@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        "David S. Miller" <davem@...emloft.net>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        Mauro Carvalho Chehab <mchehab@...nel.org>,
        Randy Dunlap <rdunlap@...radead.org>,
        devicetree@...r.kernel.org
Subject: Re: [PATCH 3/3] openrisc: dts: Add OpenRISC platform SoC

On Sun, Oct 22, 2017 at 11:46:41AM +0900, Stafford Horne wrote:
> Add devicetree binding documentation for the OpenRISC platform
> opencores,or1ksim.  This is the main OpenRISC reference platform
> supporting multiple FPGA SoC's.
> 
> This format is based on some of the mips binding docs as we have
> similar requirements.
> 
> Also, update maintainers so openrisc related binding changes are visible
> to the openrisc team.
> 

[..]

> diff --git a/MAINTAINERS b/MAINTAINERS
> index a57d13cb414d..71e4f6762196 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -10008,6 +10008,7 @@ T:	git git://github.com/openrisc/linux.git
>  L:	openrisc@...ts.librecores.org
>  W:	http://openrisc.io
>  S:	Maintained
> +F;	Documentation/devicetree/bindings/openrisc/

FYI, I found this typo (; vs :) which I have fixed and am pushing to next.

>  F:	Documentation/openrisc/
>  F:	arch/openrisc/
>  F:	drivers/irqchip/irq-or1k-*
> -- 
> 2.13.6
> 

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