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Message-Id: <20171108004449.32730-10-f.fainelli@gmail.com>
Date: Tue, 7 Nov 2017 16:44:46 -0800
From: Florian Fainelli <f.fainelli@...il.com>
To: linux-kernel@...r.kernel.org
Cc: Florian Fainelli <f.fainelli@...il.com>,
Matt Mackall <mpm@...enic.com>,
Herbert Xu <herbert@...dor.apana.org.au>,
Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Ray Jui <rjui@...adcom.com>,
Scott Branden <sbranden@...adcom.com>,
bcm-kernel-feedback-list@...adcom.com (maintainer:BROADCOM
BCM281XX/BCM11XXX/BCM216XX ARM ARCHITE...),
Eric Anholt <eric@...olt.net>,
Stefan Wahren <stefan.wahren@...e.com>,
PrasannaKumar Muralidharan <prasannatsmkumar@...il.com>,
Russell King <rmk+kernel@...linux.org.uk>,
Krzysztof Kozlowski <krzk@...nel.org>,
Harald Freudenberger <freude@...ux.vnet.ibm.com>,
Sean Wang <sean.wang@...iatek.com>,
Martin Kaiser <martin@...ser.cx>,
Steffen Trumtrar <s.trumtrar@...gutronix.de>,
linux-crypto@...r.kernel.org (open list:HARDWARE RANDOM NUMBER
GENERATOR CORE),
devicetree@...r.kernel.org (open list:OPEN FIRMWARE AND FLATTENED
DEVICE TREE BINDINGS),
linux-rpi-kernel@...ts.infradead.org (moderated list:BROADCOM BCM2835
ARM ARCHITECTURE),
linux-arm-kernel@...ts.infradead.org (moderated list:BROADCOM BCM2835
ARM ARCHITECTURE)
Subject: [PATCH v2 09/12] hwrng: bcm2835-rng: Add Broadcom MIPS I/O accessors
Broadcom MIPS HW is always strapped to match the system-wide endian such
that all I/O access to this RNG block is done with the native CPU
endian, account for that.
Signed-off-by: Florian Fainelli <f.fainelli@...il.com>
---
drivers/char/hw_random/bcm2835-rng.c | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/char/hw_random/bcm2835-rng.c b/drivers/char/hw_random/bcm2835-rng.c
index 3a607472687d..6dd8f48701b5 100644
--- a/drivers/char/hw_random/bcm2835-rng.c
+++ b/drivers/char/hw_random/bcm2835-rng.c
@@ -44,13 +44,22 @@ static inline struct bcm2835_rng_priv *to_rng_priv(struct hwrng *rng)
static inline u32 rng_readl(struct bcm2835_rng_priv *priv, u32 offset)
{
- return readl(priv->base + offset);
+ /* MIPS chips strapped for BE will automagically configure the
+ * peripheral registers for CPU-native byte order.
+ */
+ if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
+ return __raw_readl(priv->base + offset);
+ else
+ return readl(priv->base + offset);
}
static inline void rng_writel(struct bcm2835_rng_priv *priv, u32 val,
u32 offset)
{
- writel(val, priv->base + offset);
+ if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
+ __raw_writel(val, priv->base + offset);
+ else
+ writel(val, priv->base + offset);
}
static int bcm2835_rng_read(struct hwrng *rng, void *buf, size_t max,
--
2.9.3
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