lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening PHC | |
Open Source and information security mailing list archives
| ||
|
Date: Thu, 9 Nov 2017 11:48:53 +0000 From: Marc Zyngier <marc.zyngier@....com> To: Thomas Gleixner <tglx@...utronix.de> Cc: Amit Kama <amit.kama@...ixfy.com>, Ard Biesheuvel <ard.biesheuvel@...aro.org>, Ludovic Barre <ludovic.barre@...com>, Matt Redfearn <matt.redfearn@...s.com>, Paul Burton <paul.burton@...s.com>, Rob Herring <robh@...nel.org>, Jason Cooper <jason@...edaemon.net>, linux-kernel@...r.kernel.org Subject: [GIT PULL] irqchip updates for 4.15, take 3 Hi Thomas, This is the third and final pile of updates from the irqchip madhouse. On the menu, the STM32 update that has been lingering on the list for a while, yet another Socionext irqchip driver, a fix for a GICv4 facepalm bug, and a last minute MIPS cleanup. >From now on, I'm only taking bug fixes. Please pull. M. The following changes since commit 61dc367e5d767e1c56147f6e497d13cc2771abb1: irqchip: mips-gic: Make IPI bitmaps static (2017-11-02 15:55:48 +0000) are available in the git repository at: git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git tags/irqchip-4.15-3 for you to fetch changes up to 666740fde412567aa0a8ea251ffee3004a6fa3a6: irqchip: mips-gic: Print warning if inherited GIC base is used (2017-11-09 11:35:28 +0000) ---------------------------------------------------------------- irqchip updates for 4.15, take #3 - New Socionext Synquacer EXIU driver - stm32 new platform support and fixes - One GICv4 bugfix - A couple of MIPS GIC cleanups ---------------------------------------------------------------- Ard Biesheuvel (2): dt-bindings: Add description of Socionext EXIU interrupt controller irqchip/exiu: Add support for Socionext Synquacer EXIU controller Ludovic Barre (6): irqchip/stm32: Select GENERIC_IRQ_CHIP irqchip/stm32: Add multi-bank management dt-bindings/interrupt-controllers: Add compatible string for stm32h7 irqchip/stm32: Add stm32h7 support irqchip/stm32: Fix initial values irqchip/stm32: Move the wakeup on interrupt mask Marc Zyngier (1): irqchip/gic-v3-its: Fix VPE activate callback return value Matt Redfearn (2): irqchip/mips-gic: Add pr_fmt and reword pr_* messages irqchip: mips-gic: Print warning if inherited GIC base is used .../socionext,synquacer-exiu.txt | 32 +++ .../interrupt-controller/st,stm32-exti.txt | 4 +- arch/arm64/Kconfig.platforms | 3 + drivers/irqchip/Kconfig | 1 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-gic-v3-its.c | 2 +- drivers/irqchip/irq-mips-gic.c | 13 +- drivers/irqchip/irq-sni-exiu.c | 227 +++++++++++++++++++++ drivers/irqchip/irq-stm32-exti.c | 206 ++++++++++++++----- 9 files changed, 434 insertions(+), 55 deletions(-) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/socionext,synquacer-exiu.txt create mode 100644 drivers/irqchip/irq-sni-exiu.c
Powered by blists - more mailing lists