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Message-ID: <20171110214535.r3rp4g4ypj5spmue@rob-hp-laptop>
Date: Fri, 10 Nov 2017 15:45:35 -0600
From: Rob Herring <robh@...nel.org>
To: andy.tang@....com
Cc: mturquette@...libre.com, sboyd@...eaurora.org,
mark.rutland@....com, linux-clk@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] clk: qoriq: add more divider clocks support
On Wed, Nov 08, 2017 at 04:26:15PM +0800, andy.tang@....com wrote:
> From: Yuantian Tang <andy.tang@....com>
>
> More divider clocks are needed by IP. So enlarge the PLL divider
> array to accommodate more divider clocks.
>
> Signed-off-by: Tang Yuantian <andy.tang@....com>
> ---
> Documentation/devicetree/bindings/clock/qoriq-clock.txt | 1 +
> drivers/clk/clk-qoriq.c | 9 ++++++++-
> 2 files changed, 9 insertions(+), 1 deletion(-)
Acked-by: Rob Herring <robh@...nel.org>
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