linux-kernel - Re: [PATCH 21/30] x86, mm: put mmu-to-h/w ASID translation in one place

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Message-ID: <101307eb-b924-69ef-13dd-05e63fbaf587@linux.intel.com>
Date:   Fri, 10 Nov 2017 14:09:06 -0800
From:   Dave Hansen <dave.hansen@...ux.intel.com>
To:     Andy Lutomirski <luto@...nel.org>
Cc:     "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "linux-mm@...ck.org" <linux-mm@...ck.org>,
        moritz.lipp@...k.tugraz.at,
        Daniel Gruss <daniel.gruss@...k.tugraz.at>,
        michael.schwarz@...k.tugraz.at, richard.fellner@...dent.tugraz.at,
        Linus Torvalds <torvalds@...ux-foundation.org>,
        Kees Cook <keescook@...gle.com>,
        Hugh Dickins <hughd@...gle.com>, X86 ML <x86@...nel.org>
Subject: Re: [PATCH 21/30] x86, mm: put mmu-to-h/w ASID translation in one
 place

On 11/10/2017 02:03 PM, Andy Lutomirski wrote:
>> +static inline u16 kern_asid(u16 asid)
>> +{
>> +       VM_WARN_ON_ONCE(asid > MAX_ASID_AVAILABLE);
>> +       /*
>> +        * If PCID is on, ASID-aware code paths put the ASID+1 into the PCID
>> +        * bits.  This serves two purposes.  It prevents a nasty situation in
>> +        * which PCID-unaware code saves CR3, loads some other value (with PCID
>> +        * == 0), and then restores CR3, thus corrupting the TLB for ASID 0 if
>> +        * the saved ASID was nonzero.  It also means that any bugs involving
>> +        * loading a PCID-enabled CR3 with CR4.PCIDE off will trigger
>> +        * deterministically.
>> +        */
>> +       return asid + 1;
>> +}
> This seems really error-prone.  Maybe we should have a pcid_t type and
> make all the interfaces that want a h/w PCID take pcid_t.

Yeah, totally agree.  I actually had a nasty bug or two around this area
because of this.

I divided them among hw_asid_t and sw_asid_t.  You can turn a sw_asid_t
into a kernel hw_asid_t or a user hw_asid_t.  But, it cause too much
churn across the TLB flushing code so I shelved it for now.

I'd love to come back nd fix this up properly though.