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Date:   Fri, 10 Nov 2017 18:44:51 -0800
From:   Stephen Boyd <>
To:     Guodong Xu <>
Subject: Re: [PATCH] clk: hi3660: fix incorrect uart3 clock freqency

On 08/07, Guodong Xu wrote:
> From: Zhong Kaihua <>
> UART3 clock rate is doubled in previous commit.
> This error is not detected until recently a mezzanine board which makes
> real use of uart3 port (through LS connector of 96boards) was setup
> and tested on hi3660-hikey960 board.
> This patch changes clock source rate of clk_factor_uart3 to 100000000.
> Signed-off-by: Zhong Kaihua <>
> Signed-off-by: Guodong Xu <>
> ---

Applied to clk-next

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