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Message-Id: <20171113125621.983642234@linuxfoundation.org>
Date:   Mon, 13 Nov 2017 13:56:32 +0100
From:   Greg Kroah-Hartman <gregkh@...uxfoundation.org>
To:     linux-kernel@...r.kernel.org
Cc:     Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        stable@...r.kernel.org,
        Oswald Buddenhagen <oswald.buddenhagen@....de>,
        Jonas Gorski <jonas.gorski@...il.com>,
        Florian Fainelli <f.fainelli@...il.com>,
        Ralf Baechle <ralf@...ux-mips.org>,
        Yoshihiro YUNOMAE <yoshihiro.yunomae.ez@...achi.com>,
        Nicolas Schichan <nschichan@...ebox.fr>,
        linux-mips@...ux-mips.org, linux-serial@...r.kernel.org,
        James Hogan <jhogan@...nel.org>
Subject: [PATCH 4.9 75/87] MIPS: AR7: Ensure that serial ports are properly set up

4.9-stable review patch.  If anyone has any objections, please let me know.

------------------

From: Oswald Buddenhagen <oswald.buddenhagen@....de>

commit b084116f8587b222a2c5ef6dcd846f40f24b9420 upstream.

Without UPF_FIXED_TYPE, the data from the PORT_AR7 uart_config entry is
never copied, resulting in a dead port.

Fixes: 154615d55459 ("MIPS: AR7: Use correct UART port type")
Signed-off-by: Oswald Buddenhagen <oswald.buddenhagen@....de>
[jonas.gorski: add Fixes tag]
Signed-off-by: Jonas Gorski <jonas.gorski@...il.com>
Reviewed-by: Florian Fainelli <f.fainelli@...il.com>
Cc: Ralf Baechle <ralf@...ux-mips.org>
Cc: Greg Kroah-Hartman <gregkh@...uxfoundation.org>
Cc: Yoshihiro YUNOMAE <yoshihiro.yunomae.ez@...achi.com>
Cc: Nicolas Schichan <nschichan@...ebox.fr>
Cc: Oswald Buddenhagen <oswald.buddenhagen@....de>
Cc: linux-mips@...ux-mips.org
Cc: linux-serial@...r.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/17543/
Signed-off-by: James Hogan <jhogan@...nel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@...uxfoundation.org>

---
 arch/mips/ar7/platform.c |    1 +
 1 file changed, 1 insertion(+)

--- a/arch/mips/ar7/platform.c
+++ b/arch/mips/ar7/platform.c
@@ -576,6 +576,7 @@ static int __init ar7_register_uarts(voi
 	uart_port.type		= PORT_AR7;
 	uart_port.uartclk	= clk_get_rate(bus_clk) / 2;
 	uart_port.iotype	= UPIO_MEM32;
+	uart_port.flags		= UPF_FIXED_TYPE;
 	uart_port.regshift	= 2;
 
 	uart_port.line		= 0;


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